From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH v7 19/27] tcg/tci: Implement extract, sextract
Date: Tue, 1 Jun 2021 08:00:58 -0700 [thread overview]
Message-ID: <20210601150106.12761-20-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210601150106.12761-1-richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 8 ++++----
tcg/tci.c | 42 ++++++++++++++++++++++++++++++++++++++++
tcg/tci/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++
3 files changed, 78 insertions(+), 4 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 5945272a43..60b67b196b 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -69,8 +69,8 @@
#define TCG_TARGET_HAS_ext16u_i32 1
#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_deposit_i32 1
-#define TCG_TARGET_HAS_extract_i32 0
-#define TCG_TARGET_HAS_sextract_i32 0
+#define TCG_TARGET_HAS_extract_i32 1
+#define TCG_TARGET_HAS_sextract_i32 1
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 1
@@ -97,8 +97,8 @@
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_deposit_i64 1
-#define TCG_TARGET_HAS_extract_i64 0
-#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract_i64 1
+#define TCG_TARGET_HAS_sextract_i64 1
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 1
diff --git a/tcg/tci.c b/tcg/tci.c
index 068ee8f1f4..22ee32bc24 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -124,6 +124,15 @@ static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2)
*i2 = sextract32(insn, 16, 16);
}
+static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1,
+ uint8_t *i2, uint8_t *i3)
+{
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *i2 = extract32(insn, 16, 6);
+ *i3 = extract32(insn, 22, 6);
+}
+
static void tci_args_rrrc(uint32_t insn,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3)
{
@@ -608,6 +617,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
regs[r0] = deposit32(regs[r1], pos, len, regs[r2]);
break;
+#endif
+#if TCG_TARGET_HAS_extract_i32
+ case INDEX_op_extract_i32:
+ tci_args_rrbb(insn, &r0, &r1, &pos, &len);
+ regs[r0] = extract32(regs[r1], pos, len);
+ break;
+#endif
+#if TCG_TARGET_HAS_sextract_i32
+ case INDEX_op_sextract_i32:
+ tci_args_rrbb(insn, &r0, &r1, &pos, &len);
+ regs[r0] = sextract32(regs[r1], pos, len);
+ break;
#endif
case INDEX_op_brcond_i32:
tci_args_rl(insn, tb_ptr, &r0, &ptr);
@@ -748,6 +769,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
regs[r0] = deposit64(regs[r1], pos, len, regs[r2]);
break;
+#endif
+#if TCG_TARGET_HAS_extract_i64
+ case INDEX_op_extract_i64:
+ tci_args_rrbb(insn, &r0, &r1, &pos, &len);
+ regs[r0] = extract64(regs[r1], pos, len);
+ break;
+#endif
+#if TCG_TARGET_HAS_sextract_i64
+ case INDEX_op_sextract_i64:
+ tci_args_rrbb(insn, &r0, &r1, &pos, &len);
+ regs[r0] = sextract64(regs[r1], pos, len);
+ break;
#endif
case INDEX_op_brcond_i64:
tci_args_rl(insn, tb_ptr, &r0, &ptr);
@@ -1189,6 +1222,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
op_name, str_r(r0), str_r(r1), str_r(r2), pos, len);
break;
+ case INDEX_op_extract_i32:
+ case INDEX_op_extract_i64:
+ case INDEX_op_sextract_i32:
+ case INDEX_op_sextract_i64:
+ tci_args_rrbb(insn, &r0, &r1, &pos, &len);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d",
+ op_name, str_r(r0), str_r(r1), pos, len);
+ break;
+
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
case INDEX_op_setcond2_i32:
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index e7a07c1811..677ae2dceb 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -63,6 +63,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
+ case INDEX_op_extract_i32:
+ case INDEX_op_extract_i64:
+ case INDEX_op_sextract_i32:
+ case INDEX_op_sextract_i64:
return C_O1_I1(r, r);
case INDEX_op_st8_i32:
@@ -352,6 +356,21 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
tcg_out32(s, insn);
}
+static void tcg_out_op_rrbb(TCGContext *s, TCGOpcode op, TCGReg r0,
+ TCGReg r1, uint8_t b2, uint8_t b3)
+{
+ tcg_insn_unit insn = 0;
+
+ tcg_debug_assert(b2 == extract32(b2, 0, 6));
+ tcg_debug_assert(b3 == extract32(b3, 0, 6));
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 6, b2);
+ insn = deposit32(insn, 22, 6, b3);
+ tcg_out32(s, insn);
+}
+
static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3)
{
@@ -651,6 +670,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ CASE_32_64(extract) /* Optional (TCG_TARGET_HAS_extract_*). */
+ CASE_32_64(sextract) /* Optional (TCG_TARGET_HAS_sextract_*). */
+ {
+ TCGArg pos = args[2], len = args[3];
+ TCGArg max = tcg_op_defs[opc].flags & TCG_OPF_64BIT ? 64 : 32;
+
+ tcg_debug_assert(pos < max);
+ tcg_debug_assert(pos + len <= max);
+
+ tcg_out_op_rrbb(s, opc, args[0], args[1], pos, len);
+ }
+ break;
+
CASE_32_64(brcond)
tcg_out_op_rrrc(s, (opc == INDEX_op_brcond_i32
? INDEX_op_setcond_i32 : INDEX_op_setcond_i64),
--
2.25.1
next prev parent reply other threads:[~2021-06-01 15:14 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
2021-06-01 15:00 ` [PATCH v7 01/27] tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode Richard Henderson
2021-06-01 15:00 ` [PATCH v7 02/27] tcg: Add tcg_call_flags Richard Henderson
2021-06-01 15:00 ` [PATCH v7 03/27] accel/tcg/plugin-gen: Drop inline markers Richard Henderson
2021-06-01 15:00 ` [PATCH v7 04/27] plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb Richard Henderson
2021-06-02 9:22 ` Alex Bennée
2021-06-02 16:02 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 05/27] accel/tcg: Add tcg call flags to plugins helpers Richard Henderson
2021-06-01 15:00 ` [PATCH v7 06/27] tcg: Store the TCGHelperInfo in the TCGOp for call Richard Henderson
2021-06-01 15:00 ` [PATCH v7 07/27] tcg: Add tcg_call_func Richard Henderson
2021-06-01 15:00 ` [PATCH v7 08/27] tcg: Build ffi data structures for helpers Richard Henderson
2021-06-01 15:00 ` [PATCH v7 09/27] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
2021-06-02 17:59 ` Philippe Mathieu-Daudé
2021-06-01 15:00 ` [PATCH v7 10/27] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
2021-06-01 15:00 ` [PATCH v7 11/27] tcg/tci: Use ffi for calls Richard Henderson
2021-06-02 10:31 ` Alex Bennée
2021-06-01 15:00 ` [PATCH v7 12/27] tcg/tci: Reserve r13 for a temporary Richard Henderson
2021-06-19 15:50 ` Philippe Mathieu-Daudé
2021-06-01 15:00 ` [PATCH v7 13/27] tcg/tci: Emit setcond before brcond Richard Henderson
2021-06-19 15:50 ` Philippe Mathieu-Daudé
2021-06-01 15:00 ` [PATCH v7 14/27] tcg/tci: Remove tci_write_reg Richard Henderson
2021-06-01 15:00 ` [PATCH v7 15/27] tcg/tci: Change encoding to uint32_t units Richard Henderson
2021-06-12 10:21 ` Philippe Mathieu-Daudé
2021-06-12 15:40 ` Richard Henderson
2021-06-19 17:48 ` Philippe Mathieu-Daudé
2021-06-19 18:05 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 16/27] tcg/tci: Implement goto_ptr Richard Henderson
2021-06-12 9:45 ` Philippe Mathieu-Daudé
2021-06-01 15:00 ` [PATCH v7 17/27] tcg/tci: Implement movcond Richard Henderson
2021-06-01 15:00 ` [PATCH v7 18/27] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
2021-06-01 15:00 ` Richard Henderson [this message]
2021-06-01 15:00 ` [PATCH v7 20/27] tcg/tci: Implement clz, ctz, ctpop Richard Henderson
2021-06-01 15:01 ` [PATCH v7 21/27] tcg/tci: Implement mulu2, muls2 Richard Henderson
2021-06-01 15:01 ` [PATCH v7 22/27] tcg/tci: Implement add2, sub2 Richard Henderson
2021-06-12 9:36 ` Philippe Mathieu-Daudé
2021-06-01 15:01 ` [PATCH v7 23/27] tcg/tci: Split out tci_qemu_ld, tci_qemu_st Richard Henderson
2021-06-02 18:01 ` Philippe Mathieu-Daudé
2021-06-01 15:01 ` [PATCH v7 24/27] Revert "tcg/tci: Use exec/cpu_ldst.h interfaces" Richard Henderson
2021-06-12 9:24 ` Philippe Mathieu-Daudé
2021-06-01 15:01 ` [PATCH v7 25/27] tcg/tci: Remove the qemu_ld/st_type macros Richard Henderson
2021-06-02 18:03 ` Philippe Mathieu-Daudé
2021-06-01 15:01 ` [PATCH v7 26/27] tcg/tci: Use {set,clear}_helper_retaddr Richard Henderson
2021-06-12 9:24 ` Philippe Mathieu-Daudé
2021-06-01 15:01 ` [PATCH v7 27/27] tests/tcg: Increase timeout for TCI Richard Henderson
2021-06-02 9:26 ` Alex Bennée
2021-06-01 15:30 ` [PATCH v7 00/27] TCI fixes and cleanups no-reply
2021-06-19 17:42 ` Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210601150106.12761-20-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=f4bug@amsat.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.