From: Sergiy Kibrik <Sergiy_Kibrik@epam.com>
To: xen-devel@lists.xenproject.org
Cc: "Sergiy Kibrik" <Sergiy_Kibrik@epam.com>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Roger Pau Monné" <roger.pau@citrix.com>,
"Jan Beulich" <jbeulich@suse.com>,
"Stefano Stabellini" <sstabellini@kernel.org>
Subject: [XEN PATCH v3 6/6] x86/MCE: optional build of AMD/Intel MCE code
Date: Tue, 14 May 2024 11:28:39 +0300 [thread overview]
Message-ID: <def311f3206f29f919a921d459442641fc293031.1715673586.git.Sergiy_Kibrik@epam.com> (raw)
In-Reply-To: <cover.1715673586.git.Sergiy_Kibrik@epam.com>
Separate Intel/AMD-specific MCE code using CONFIG_{INTEL,AMD} config options.
Now we can avoid build of mcheck code if support for specific platform is
intentionally disabled by configuration.
Also global variables lmce_support & cmci_support from Intel-specific
mce_intel.c have to moved to common mce.c, as they get checked in common code.
Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@epam.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
CC: Jan Beulich <jbeulich@suse.com>
---
changes in v3:
- default return value of init_nonfatal_mce_checker() done in separate patch
- move lmce_support & cmci_support to common mce.c code
- changed patch description
changes in v2:
- fallback to original ordering in Makefile
- redefine lmce_support & cmci_support global vars to false when !INTEL
- changed patch description
---
xen/arch/x86/cpu/mcheck/Makefile | 8 ++++----
xen/arch/x86/cpu/mcheck/mce.c | 4 ++++
xen/arch/x86/cpu/mcheck/mce_intel.c | 4 ----
xen/arch/x86/cpu/mcheck/non-fatal.c | 4 ++++
4 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/xen/arch/x86/cpu/mcheck/Makefile b/xen/arch/x86/cpu/mcheck/Makefile
index f927f10b4d..e6cb4dd503 100644
--- a/xen/arch/x86/cpu/mcheck/Makefile
+++ b/xen/arch/x86/cpu/mcheck/Makefile
@@ -1,12 +1,12 @@
-obj-y += amd_nonfatal.o
-obj-y += mce_amd.o
+obj-$(CONFIG_AMD) += amd_nonfatal.o
+obj-$(CONFIG_AMD) += mce_amd.o
obj-y += mcaction.o
obj-y += barrier.o
-obj-y += intel-nonfatal.o
+obj-$(CONFIG_INTEL) += intel-nonfatal.o
obj-y += mctelem.o
obj-y += mce.o
obj-y += mce-apei.o
-obj-y += mce_intel.o
+obj-$(CONFIG_INTEL) += mce_intel.o
obj-y += non-fatal.o
obj-y += util.o
obj-y += vmce.o
diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c
index fb9dec5b89..32c1b2756b 100644
--- a/xen/arch/x86/cpu/mcheck/mce.c
+++ b/xen/arch/x86/cpu/mcheck/mce.c
@@ -38,6 +38,10 @@ DEFINE_PER_CPU_READ_MOSTLY(unsigned int, nr_mce_banks);
unsigned int __read_mostly firstbank;
unsigned int __read_mostly ppin_msr;
uint8_t __read_mostly cmci_apic_vector;
+bool __read_mostly cmci_support;
+
+/* If mce_force_broadcast == 1, lmce_support will be disabled forcibly. */
+bool __read_mostly lmce_support;
DEFINE_PER_CPU_READ_MOSTLY(struct mca_banks *, poll_bankmask);
DEFINE_PER_CPU_READ_MOSTLY(struct mca_banks *, no_cmci_banks);
diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c
index af43281cc6..dd812f4b8a 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -26,16 +26,12 @@
#include "mcaction.h"
static DEFINE_PER_CPU_READ_MOSTLY(struct mca_banks *, mce_banks_owned);
-bool __read_mostly cmci_support;
static bool __read_mostly ser_support;
static bool __read_mostly mce_force_broadcast;
boolean_param("mce_fb", mce_force_broadcast);
static int __read_mostly nr_intel_ext_msrs;
-/* If mce_force_broadcast == 1, lmce_support will be disabled forcibly. */
-bool __read_mostly lmce_support;
-
/* Intel SDM define bit15~bit0 of IA32_MCi_STATUS as the MC error code */
#define INTEL_MCCOD_MASK 0xFFFF
diff --git a/xen/arch/x86/cpu/mcheck/non-fatal.c b/xen/arch/x86/cpu/mcheck/non-fatal.c
index c5d8e3aea9..52e16ad499 100644
--- a/xen/arch/x86/cpu/mcheck/non-fatal.c
+++ b/xen/arch/x86/cpu/mcheck/non-fatal.c
@@ -24,15 +24,19 @@ static int __init cf_check init_nonfatal_mce_checker(void)
* Check for non-fatal errors every MCE_RATE s
*/
switch (c->x86_vendor) {
+#ifdef CONFIG_AMD
case X86_VENDOR_AMD:
case X86_VENDOR_HYGON:
/* Assume we are on K8 or newer AMD or Hygon CPU here */
amd_nonfatal_mcheck_init(c);
break;
+#endif
+#ifdef CONFIG_INTEL
case X86_VENDOR_INTEL:
intel_nonfatal_mcheck_init(c);
break;
+#endif
default:
return -ENODEV;
--
2.25.1
next prev parent reply other threads:[~2024-05-14 8:29 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-14 8:16 [XEN PATCH v3 0/6] x86: make Intel/AMD vPMU & MCE support configurable Sergiy Kibrik
2024-05-14 8:18 ` [XEN PATCH v3 1/6] x86/vpmu: separate amd/intel vPMU code Sergiy Kibrik
2024-05-14 8:20 ` [XEN PATCH v3 2/6] x86/intel: move vmce_has_lmce() routine to header Sergiy Kibrik
2024-05-16 9:39 ` Jan Beulich
2024-05-20 9:32 ` Sergiy Kibrik
2024-05-21 6:05 ` Jan Beulich
2024-05-21 10:00 ` Sergiy Kibrik
2024-05-21 10:19 ` Jan Beulich
2024-05-14 8:22 ` [XEN PATCH v3 3/6] x86/MCE: guard access to Intel/AMD-specific MCA MSRs Sergiy Kibrik
2024-05-14 8:24 ` [XEN PATCH v3 4/6] x86/MCE: guard {intel/amd}_mcheck_init() calls Sergiy Kibrik
2024-05-14 8:26 ` [XEN PATCH v3 5/6] x86/MCE: add default switch case in init_nonfatal_mce_checker() Sergiy Kibrik
2024-05-16 9:44 ` Jan Beulich
2024-05-16 9:46 ` Jan Beulich
2024-05-20 9:41 ` Sergiy Kibrik
2024-05-14 8:28 ` Sergiy Kibrik [this message]
2024-05-16 9:55 ` [XEN PATCH v3 6/6] x86/MCE: optional build of AMD/Intel MCE code Jan Beulich
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