* [PATCH 0/4] arm64: zynqmp: Update USB and Kria DTs
@ 2021-06-11 7:04 Michal Simek
2021-06-11 7:04 ` [PATCH 1/4] arm64: zynqmp: Remove revA compatibility string from kv260 revB/1 Michal Simek
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Michal Simek @ 2021-06-11 7:04 UTC (permalink / raw
To: u-boot, git
Cc: Amit Kumar Mahapatra, Michal Simek, Srinivas Neeli,
Stefano Stabellini
Hi,
this series contain updates for Kria SOM kv260 CCs. Also update usb
description.
Thanks,
Michal
Michal Simek (4):
arm64: zynqmp: Remove revA compatibility string from kv260 revB/1
arm64: zynqmp: Use overlay sugar syntax for Kria SOM
arm64: zynqmp: Update usb dwc3 DT description
arm64: zynqmp: Enable USB3.0 for dc2/dc3
arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 592 +++++++++++------------
arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 573 ++++++++++------------
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 +
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 12 +
arch/arm/dts/zynqmp.dtsi | 20 +-
5 files changed, 578 insertions(+), 621 deletions(-)
--
2.32.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/4] arm64: zynqmp: Remove revA compatibility string from kv260 revB/1
2021-06-11 7:04 [PATCH 0/4] arm64: zynqmp: Update USB and Kria DTs Michal Simek
@ 2021-06-11 7:04 ` Michal Simek
2021-06-11 7:04 ` [PATCH 2/4] arm64: zynqmp: Use overlay sugar syntax for Kria SOM Michal Simek
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Michal Simek @ 2021-06-11 7:04 UTC (permalink / raw
To: u-boot, git
kv260-revB is different compare to revA (usbhub is wired via i2c) that's
why remove revA compatible string.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index 6e46f5717b23..1393f997a012 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -17,7 +17,7 @@
/{
compatible = "xlnx,zynqmp-sk-kv260-rev1",
- "xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260-revA",
+ "xlnx,zynqmp-sk-kv260-revB",
"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
fragment1 {
--
2.32.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/4] arm64: zynqmp: Use overlay sugar syntax for Kria SOM
2021-06-11 7:04 [PATCH 0/4] arm64: zynqmp: Update USB and Kria DTs Michal Simek
2021-06-11 7:04 ` [PATCH 1/4] arm64: zynqmp: Remove revA compatibility string from kv260 revB/1 Michal Simek
@ 2021-06-11 7:04 ` Michal Simek
2021-06-11 7:04 ` [PATCH 3/4] arm64: zynqmp: Update usb dwc3 DT description Michal Simek
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Michal Simek @ 2021-06-11 7:04 UTC (permalink / raw
To: u-boot, git
dtc supports new sugar syntax which is easier compare to previous one
that's why also covert overlays for SOM to it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 592 ++++++++++++--------------
arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 571 ++++++++++++-------------
2 files changed, 545 insertions(+), 618 deletions(-)
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index cad2d0572185..cca009e7c759 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -20,354 +20,316 @@
/dts-v1/;
/plugin/;
-/{
+&{/} {
compatible = "xlnx,zynqmp-sk-kv260-revA",
"xlnx,zynqmp-sk-kv260-revY",
"xlnx,zynqmp-sk-kv260-revZ",
"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
+};
- fragment1 {
- target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
-
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1_default>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
-
- u14: ina260@40 { /* u14 */
- compatible = "ti,ina260";
- #io-channel-cells = <1>;
- label = "ina260-u14";
- reg = <0x40>;
- };
- /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
- };
+&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+
+ u14: ina260@40 { /* u14 */
+ compatible = "ti,ina260";
+ #io-channel-cells = <1>;
+ label = "ina260-u14";
+ reg = <0x40>;
};
+ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
+};
- fragment1a {
- target = <&amba>;
- __overlay__ {
- ina260-u14 {
- compatible = "iio-hwmon";
- io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
- };
-
- si5332_0: si5332_0 { /* u17 */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>;
- };
-
- si5332_1: si5332_1 { /* u17 */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- si5332_2: si5332_2 { /* u17 */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
-
- si5332_3: si5332_3 { /* u17 */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- };
-
- si5332_4: si5332_4 { /* u17 */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <26000000>;
- };
-
- si5332_5: si5332_5 { /* u17 */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <27000000>;
- };
- };
+&amba {
+ ina260-u14 {
+ compatible = "iio-hwmon";
+ io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
};
+ si5332_0: si5332_0 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ si5332_1: si5332_1 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ si5332_2: si5332_2 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ si5332_3: si5332_3 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ si5332_4: si5332_4 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ si5332_5: si5332_5 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+};
+
/* DP/USB 3.0 and SATA */
- fragment2 {
- target = <&psgtr>;
- __overlay__ {
- status = "okay";
- /* pcie, usb3, sata */
- clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
- clock-names = "ref0", "ref1", "ref2";
- };
+&psgtr {
+ status = "okay";
+ /* pcie, usb3, sata */
+ clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
+ clock-names = "ref0", "ref1", "ref2";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
+};
+
+&zynqmp_dpsub {
+ status = "disabled";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+};
+
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ usbhub: usb5744 { /* u43 */
+ compatible = "microchip,usb5744";
+ reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
};
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+ maximum-speed = "super-speed";
+};
+
+&sdhci1 { /* on CC with tuned parameters */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
+ /*
+ * SD 3.0 requires level shifter and this property
+ * should be removed if the board has level shifter and
+ * need to work in UHS mode
+ */
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio-bank = <1>;
+};
- fragment3 {
- target = <&sata>;
- __overlay__ {
- status = "okay";
- /* SATA OOB timing settings */
- ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
- ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
- ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
- ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
- ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
- ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
- ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
- ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
- phy-names = "sata-phy";
- phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
+&gem3 { /* required by spec */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>;
+
+ phy0: ethernet-phy@1 {
+ #phy-cells = <1>;
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
};
};
+};
- fragment4 {
- target = <&zynqmp_dpsub>;
- __overlay__ {
- status = "disabled";
- phy-names = "dp-phy0", "dp-phy1";
- phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+&pinctrl0 { /* required by spec */
+ status = "okay";
+
+ pinctrl_uart1_default: uart1-default {
+ conf {
+ groups = "uart1_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
};
- };
- fragment9 {
- target = <&zynqmp_dpdma>;
- __overlay__ {
- status = "okay";
+ conf-rx {
+ pins = "MIO37";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO36";
+ bias-disable;
};
- };
- fragment10 {
- target = <&usb0>;
- __overlay__ {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0_default>;
- usbhub: usb5744 { /* u43 */
- compatible = "microchip,usb5744";
- reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
- };
+ mux {
+ groups = "uart1_9_grp";
+ function = "uart1";
};
};
- fragment11 {
- target = <&dwc3_0>;
- __overlay__ {
- status = "okay";
- dr_mode = "host";
- snps,usb3_lpm_capable;
- phy-names = "usb3-phy";
- phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
- maximum-speed = "super-speed";
+ pinctrl_i2c1_default: i2c1-default {
+ conf {
+ groups = "i2c1_6_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "i2c1_6_grp";
+ function = "i2c1";
};
};
- fragment12 {
- target = <&sdhci1>; /* on CC with tuned parameters */
- __overlay__ {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sdhci1_default>;
- /*
- * SD 3.0 requires level shifter and this property
- * should be removed if the board has level shifter and
- * need to work in UHS mode
- */
- no-1-8-v;
- disable-wp;
- xlnx,mio-bank = <1>;
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ conf {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ function = "gpio0";
};
};
- fragment13 {
- target = <&gem3>; /* required by spec */
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gem3_default>;
- phy-handle = <&phy0>;
- phy-mode = "rgmii-id";
-
- mdio: mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2>;
-
- phy0: ethernet-phy@1 {
- #phy-cells = <1>;
- reg = <1>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,dp83867-rxctrl-strap-quirk;
- };
- };
+ pinctrl_gem3_default: gem3-default {
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO72", "MIO74";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-bootstrap {
+ pins = "MIO71", "MIO73", "MIO75";
+ bias-disable;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66",
+ "MIO67", "MIO68", "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
};
};
- fragment14 {
- target = <&pinctrl0>; /* required by spec */
- __overlay__ {
- status = "okay";
-
- pinctrl_uart1_default: uart1-default {
- conf {
- groups = "uart1_9_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- drive-strength = <12>;
- };
-
- conf-rx {
- pins = "MIO37";
- bias-high-impedance;
- };
-
- conf-tx {
- pins = "MIO36";
- bias-disable;
- };
-
- mux {
- groups = "uart1_9_grp";
- function = "uart1";
- };
- };
-
- pinctrl_i2c1_default: i2c1-default {
- conf {
- groups = "i2c1_6_grp";
- bias-pull-up;
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- };
-
- mux {
- groups = "i2c1_6_grp";
- function = "i2c1";
- };
- };
-
- pinctrl_i2c1_gpio: i2c1-gpio {
- conf {
- groups = "gpio0_24_grp", "gpio0_25_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- };
-
- mux {
- groups = "gpio0_24_grp", "gpio0_25_grp";
- function = "gpio0";
- };
- };
-
- pinctrl_gem3_default: gem3-default {
- conf {
- groups = "ethernet3_0_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- };
-
- conf-rx {
- pins = "MIO70", "MIO72", "MIO74";
- bias-high-impedance;
- low-power-disable;
- };
-
- conf-bootstrap {
- pins = "MIO71", "MIO73", "MIO75";
- bias-disable;
- low-power-disable;
- };
-
- conf-tx {
- pins = "MIO64", "MIO65", "MIO66",
- "MIO67", "MIO68", "MIO69";
- bias-disable;
- low-power-enable;
- };
-
- conf-mdio {
- groups = "mdio3_0_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- bias-disable;
- };
-
- mux-mdio {
- function = "mdio3";
- groups = "mdio3_0_grp";
- };
-
- mux {
- function = "ethernet3";
- groups = "ethernet3_0_grp";
- };
- };
-
- pinctrl_usb0_default: usb0-default {
- conf {
- groups = "usb0_0_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- };
-
- conf-rx {
- pins = "MIO52", "MIO53", "MIO55";
- bias-high-impedance;
- };
-
- conf-tx {
- pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
- "MIO60", "MIO61", "MIO62", "MIO63";
- bias-disable;
- };
-
- mux {
- groups = "usb0_0_grp";
- function = "usb0";
- };
- };
-
- pinctrl_sdhci1_default: sdhci1-default {
- conf {
- groups = "sdio1_0_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- bias-disable;
- };
-
- conf-cd {
- groups = "sdio1_cd_0_grp";
- bias-high-impedance;
- bias-pull-up;
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- };
-
- mux-cd {
- groups = "sdio1_cd_0_grp";
- function = "sdio1_cd";
- };
-
- mux {
- groups = "sdio1_0_grp";
- function = "sdio1";
- };
- };
+ pinctrl_usb0_default: usb0-default {
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
};
};
- fragment15 {
- target = <&uart1>;
- __overlay__ {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1_default>;
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
};
};
};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+};
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index 1393f997a012..d004ad143954 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -15,339 +15,304 @@
/dts-v1/;
/plugin/;
-/{
+&{/} {
compatible = "xlnx,zynqmp-sk-kv260-rev1",
"xlnx,zynqmp-sk-kv260-revB",
"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
+};
- fragment1 {
- target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
-
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1_default>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
-
- u14: ina260@40 { /* u14 */
- compatible = "ti,ina260";
- #io-channel-cells = <1>;
- label = "ina260-u14";
- reg = <0x40>;
- };
- usbhub: usb5744@2d { /* u43 */
- compatible = "microchip,usb5744";
- reg = <0x2d>;
- reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
- };
- /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
- };
+&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+
+ u14: ina260@40 { /* u14 */
+ compatible = "ti,ina260";
+ #io-channel-cells = <1>;
+ label = "ina260-u14";
+ reg = <0x40>;
+ };
+ usbhub: usb5744@2d { /* u43 */
+ compatible = "microchip,usb5744";
+ reg = <0x2d>;
+ reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
};
+ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
+};
- fragment1a {
- target = <&amba>;
- __overlay__ {
- ina260-u14 {
- compatible = "iio-hwmon";
- io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
- };
-
- si5332_0: si5332_0 { /* u17 */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>;
- };
-
- si5332_1: si5332_1 { /* u17 */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- si5332_2: si5332_2 { /* u17 */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
-
- si5332_3: si5332_3 { /* u17 */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- };
-
- si5332_4: si5332_4 { /* u17 */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <26000000>;
- };
-
- si5332_5: si5332_5 { /* u17 */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <27000000>;
- };
- };
+&amba {
+ ina260-u14 {
+ compatible = "iio-hwmon";
+ io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
+ };
+
+ si5332_0: si5332_0 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ si5332_1: si5332_1 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ si5332_2: si5332_2 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ si5332_3: si5332_3 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ si5332_4: si5332_4 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ si5332_5: si5332_5 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
};
+};
/* DP/USB 3.0 */
- fragment2 {
- target = <&psgtr>;
- __overlay__ {
- status = "okay";
- /* pcie, usb3, sata */
- clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
- clock-names = "ref0", "ref1", "ref2";
+&psgtr {
+ status = "okay";
+ /* pcie, usb3, sata */
+ clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
+ clock-names = "ref0", "ref1", "ref2";
+};
+
+&zynqmp_dpsub {
+ status = "disabled";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+};
+
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+ maximum-speed = "super-speed";
+};
+
+&sdhci1 { /* on CC with tuned parameters */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
+ /*
+ * SD 3.0 requires level shifter and this property
+ * should be removed if the board has level shifter and
+ * need to work in UHS mode
+ */
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio-bank = <1>;
+ clk-phase-sd-hs = <126>, <60>;
+ clk-phase-uhs-sdr25 = <120>, <60>;
+ clk-phase-uhs-ddr50 = <126>, <48>;
+};
+
+&gem3 { /* required by spec */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>;
+
+ phy0: ethernet-phy@1 {
+ #phy-cells = <1>;
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
};
};
+};
+
+&pinctrl0 { /* required by spec */
+ status = "okay";
- fragment4 {
- target = <&zynqmp_dpsub>;
- __overlay__ {
- status = "disabled";
- phy-names = "dp-phy0", "dp-phy1";
- phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+ pinctrl_uart1_default: uart1-default {
+ conf {
+ groups = "uart1_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
};
- };
- fragment9 {
- target = <&zynqmp_dpdma>;
- __overlay__ {
- status = "okay";
+ conf-rx {
+ pins = "MIO37";
+ bias-high-impedance;
};
- };
- fragment10 {
- target = <&usb0>;
- __overlay__ {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0_default>;
+ conf-tx {
+ pins = "MIO36";
+ bias-disable;
+ };
+
+ mux {
+ groups = "uart1_9_grp";
+ function = "uart1";
};
};
- fragment11 {
- target = <&dwc3_0>;
- __overlay__ {
- status = "okay";
- dr_mode = "host";
- snps,usb3_lpm_capable;
- phy-names = "usb3-phy";
- phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
- maximum-speed = "super-speed";
+ pinctrl_i2c1_default: i2c1-default {
+ conf {
+ groups = "i2c1_6_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "i2c1_6_grp";
+ function = "i2c1";
};
};
- fragment12 {
- target = <&sdhci1>; /* on CC with tuned parameters */
- __overlay__ {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sdhci1_default>;
- /*
- * SD 3.0 requires level shifter and this property
- * should be removed if the board has level shifter and
- * need to work in UHS mode
- */
- no-1-8-v;
- disable-wp;
- xlnx,mio-bank = <1>;
- clk-phase-sd-hs = <126>, <60>;
- clk-phase-uhs-sdr25 = <120>, <60>;
- clk-phase-uhs-ddr50 = <126>, <48>;
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ conf {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ function = "gpio0";
};
};
- fragment13 {
- target = <&gem3>; /* required by spec */
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gem3_default>;
- phy-handle = <&phy0>;
- phy-mode = "rgmii-id";
-
- mdio: mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2>;
-
- phy0: ethernet-phy@1 {
- #phy-cells = <1>;
- reg = <1>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,dp83867-rxctrl-strap-quirk;
- };
- };
+ pinctrl_gem3_default: gem3-default {
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO72", "MIO74";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-bootstrap {
+ pins = "MIO71", "MIO73", "MIO75";
+ bias-disable;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66",
+ "MIO67", "MIO68", "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
};
};
- fragment14 {
- target = <&pinctrl0>; /* required by spec */
- __overlay__ {
- status = "okay";
-
- pinctrl_uart1_default: uart1-default {
- conf {
- groups = "uart1_9_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- drive-strength = <12>;
- };
-
- conf-rx {
- pins = "MIO37";
- bias-high-impedance;
- };
-
- conf-tx {
- pins = "MIO36";
- bias-disable;
- };
-
- mux {
- groups = "uart1_9_grp";
- function = "uart1";
- };
- };
-
- pinctrl_i2c1_default: i2c1-default {
- conf {
- groups = "i2c1_6_grp";
- bias-pull-up;
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- };
-
- mux {
- groups = "i2c1_6_grp";
- function = "i2c1";
- };
- };
-
- pinctrl_i2c1_gpio: i2c1-gpio {
- conf {
- groups = "gpio0_24_grp", "gpio0_25_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- };
-
- mux {
- groups = "gpio0_24_grp", "gpio0_25_grp";
- function = "gpio0";
- };
- };
-
- pinctrl_gem3_default: gem3-default {
- conf {
- groups = "ethernet3_0_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- };
-
- conf-rx {
- pins = "MIO70", "MIO72", "MIO74";
- bias-high-impedance;
- low-power-disable;
- };
-
- conf-bootstrap {
- pins = "MIO71", "MIO73", "MIO75";
- bias-disable;
- low-power-disable;
- };
-
- conf-tx {
- pins = "MIO64", "MIO65", "MIO66",
- "MIO67", "MIO68", "MIO69";
- bias-disable;
- low-power-enable;
- };
-
- conf-mdio {
- groups = "mdio3_0_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- bias-disable;
- };
-
- mux-mdio {
- function = "mdio3";
- groups = "mdio3_0_grp";
- };
-
- mux {
- function = "ethernet3";
- groups = "ethernet3_0_grp";
- };
- };
-
- pinctrl_usb0_default: usb0-default {
- conf {
- groups = "usb0_0_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- };
-
- conf-rx {
- pins = "MIO52", "MIO53", "MIO55";
- bias-high-impedance;
- };
-
- conf-tx {
- pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
- "MIO60", "MIO61", "MIO62", "MIO63";
- bias-disable;
- };
-
- mux {
- groups = "usb0_0_grp";
- function = "usb0";
- };
- };
-
- pinctrl_sdhci1_default: sdhci1-default {
- conf {
- groups = "sdio1_0_grp";
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- bias-disable;
- };
-
- conf-cd {
- groups = "sdio1_cd_0_grp";
- bias-high-impedance;
- bias-pull-up;
- slew-rate = <SLEW_RATE_SLOW>;
- power-source = <IO_STANDARD_LVCMOS18>;
- };
-
- mux-cd {
- groups = "sdio1_cd_0_grp";
- function = "sdio1_cd";
- };
-
- mux {
- groups = "sdio1_0_grp";
- function = "sdio1";
- };
- };
+ pinctrl_usb0_default: usb0-default {
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
};
};
- fragment15 {
- target = <&uart1>;
- __overlay__ {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1_default>;
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
};
};
};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+};
--
2.32.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/4] arm64: zynqmp: Update usb dwc3 DT description
2021-06-11 7:04 [PATCH 0/4] arm64: zynqmp: Update USB and Kria DTs Michal Simek
2021-06-11 7:04 ` [PATCH 1/4] arm64: zynqmp: Remove revA compatibility string from kv260 revB/1 Michal Simek
2021-06-11 7:04 ` [PATCH 2/4] arm64: zynqmp: Use overlay sugar syntax for Kria SOM Michal Simek
@ 2021-06-11 7:04 ` Michal Simek
2021-06-11 7:04 ` [PATCH 4/4] arm64: zynqmp: Enable USB3.0 for dc2/dc3 Michal Simek
2021-06-21 7:49 ` [PATCH 0/4] arm64: zynqmp: Update USB and Kria DTs Michal Simek
4 siblings, 0 replies; 6+ messages in thread
From: Michal Simek @ 2021-06-11 7:04 UTC (permalink / raw
To: u-boot, git
Cc: Amit Kumar Mahapatra, Michal Simek, Srinivas Neeli,
Stefano Stabellini
Align USB nodes with the latest dt-bindings. It is adding resets, new
interrupt and also some quirks.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynqmp.dtsi | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 7de7166bd7fb..1332f5373fb4 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -848,6 +848,10 @@
reg = <0x0 0xff9d0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
power-domains = <&zynqmp_firmware PD_USB_0>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
+ <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
+ <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
+ reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
ranges;
dwc3_0: dwc3@fe200000 {
@@ -855,11 +859,15 @@
status = "disabled";
reg = <0x0 0xfe200000 0x0 0x40000>;
interrupt-parent = <&gic>;
- interrupts = <0 65 4>, <0 69 4>;
+ interrupt-names = "dwc_usb3", "otg", "hiber";
+ interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
#stream-id-cells = <1>;
iommus = <&smmu 0x860>;
snps,quirk-frame-length-adjustment = <0x20>;
snps,refclk_fladj;
+ snps,enable_guctl1_resume_quirk;
+ snps,enable_guctl1_ipd_quirk;
+ snps,xhci-stream-quirk;
/* dma-coherent; */
};
};
@@ -872,6 +880,10 @@
reg = <0x0 0xff9e0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
power-domains = <&zynqmp_firmware PD_USB_1>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
+ <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
+ <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
+ reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
ranges;
dwc3_1: dwc3@fe300000 {
@@ -879,11 +891,15 @@
status = "disabled";
reg = <0x0 0xfe300000 0x0 0x40000>;
interrupt-parent = <&gic>;
- interrupts = <0 70 4>, <0 74 4>;
+ interrupt-names = "dwc_usb3", "otg", "hiber";
+ interrupts = <0 70 4>, <0 74 4>, <0 76 4>;
#stream-id-cells = <1>;
iommus = <&smmu 0x861>;
snps,quirk-frame-length-adjustment = <0x20>;
snps,refclk_fladj;
+ snps,enable_guctl1_resume_quirk;
+ snps,enable_guctl1_ipd_quirk;
+ snps,xhci-stream-quirk;
/* dma-coherent; */
};
};
--
2.32.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/4] arm64: zynqmp: Enable USB3.0 for dc2/dc3
2021-06-11 7:04 [PATCH 0/4] arm64: zynqmp: Update USB and Kria DTs Michal Simek
` (2 preceding siblings ...)
2021-06-11 7:04 ` [PATCH 3/4] arm64: zynqmp: Update usb dwc3 DT description Michal Simek
@ 2021-06-11 7:04 ` Michal Simek
2021-06-21 7:49 ` [PATCH 0/4] arm64: zynqmp: Update USB and Kria DTs Michal Simek
4 siblings, 0 replies; 6+ messages in thread
From: Michal Simek @ 2021-06-11 7:04 UTC (permalink / raw
To: u-boot, git
Both boards are usb3.0 capable. dc3 was also missing enabling dwc3* nodes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 ++
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 12 ++++++++++++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 4225a9547c58..5b689dbd0937 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -535,6 +535,8 @@
&dwc3_1 {
status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
};
&uart0 {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
index 35fb33f12b6b..a9bac1dec03e 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@@ -199,11 +199,23 @@
&usb0 {
status = "okay";
+};
+
+&dwc3_0 {
+ status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
};
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
+};
+
+&dwc3_1 {
+ status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
};
--
2.32.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 0/4] arm64: zynqmp: Update USB and Kria DTs
2021-06-11 7:04 [PATCH 0/4] arm64: zynqmp: Update USB and Kria DTs Michal Simek
` (3 preceding siblings ...)
2021-06-11 7:04 ` [PATCH 4/4] arm64: zynqmp: Enable USB3.0 for dc2/dc3 Michal Simek
@ 2021-06-21 7:49 ` Michal Simek
4 siblings, 0 replies; 6+ messages in thread
From: Michal Simek @ 2021-06-21 7:49 UTC (permalink / raw
To: U-Boot, git; +Cc: Amit Kumar Mahapatra, Srinivas Neeli, Stefano Stabellini
pá 11. 6. 2021 v 9:04 odesílatel Michal Simek <michal.simek@xilinx.com> napsal:
>
> Hi,
>
> this series contain updates for Kria SOM kv260 CCs. Also update usb
> description.
>
> Thanks,
> Michal
>
>
> Michal Simek (4):
> arm64: zynqmp: Remove revA compatibility string from kv260 revB/1
> arm64: zynqmp: Use overlay sugar syntax for Kria SOM
> arm64: zynqmp: Update usb dwc3 DT description
> arm64: zynqmp: Enable USB3.0 for dc2/dc3
>
> arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 592 +++++++++++------------
> arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 573 ++++++++++------------
> arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 +
> arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 12 +
> arch/arm/dts/zynqmp.dtsi | 20 +-
> 5 files changed, 578 insertions(+), 621 deletions(-)
>
> --
> 2.32.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-06-21 7:49 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-06-11 7:04 [PATCH 0/4] arm64: zynqmp: Update USB and Kria DTs Michal Simek
2021-06-11 7:04 ` [PATCH 1/4] arm64: zynqmp: Remove revA compatibility string from kv260 revB/1 Michal Simek
2021-06-11 7:04 ` [PATCH 2/4] arm64: zynqmp: Use overlay sugar syntax for Kria SOM Michal Simek
2021-06-11 7:04 ` [PATCH 3/4] arm64: zynqmp: Update usb dwc3 DT description Michal Simek
2021-06-11 7:04 ` [PATCH 4/4] arm64: zynqmp: Enable USB3.0 for dc2/dc3 Michal Simek
2021-06-21 7:49 ` [PATCH 0/4] arm64: zynqmp: Update USB and Kria DTs Michal Simek
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).