From: Leo Liang <ycliang@andestech.com>
To: Yu Chien Peter Lin <peterlin@andestech.com>
Cc: <tim609@andestech.com>, <randolph@andestech.com>, <u-boot@lists.denx.de>
Subject: Re: [PATCH] riscv: andesv5: Set default cache line size to 64-bytes
Date: Wed, 1 May 2024 22:32:59 +0800 [thread overview]
Message-ID: <ZjJSm0iDX4ZhiWz8@swlinux02> (raw)
In-Reply-To: <20240411092945.777695-1-peterlin@andestech.com>
On Thu, Apr 11, 2024 at 05:29:45PM +0800, Yu Chien Peter Lin wrote:
> The instruction and data cache line sizes of Andes core
> are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so
> the SYS_CACHELINE_SIZE is enabled with a default value.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> arch/riscv/cpu/andesv5/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
prev parent reply other threads:[~2024-05-01 14:33 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-11 9:29 [PATCH] riscv: andesv5: Set default cache line size to 64-bytes Yu Chien Peter Lin
2024-05-01 14:32 ` Leo Liang [this message]
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