[U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support

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* [U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support
@ 2017-08-16  5:41 Bin Meng
  2017-08-16  5:41 ` [U-Boot] [PATCH 01/13] x86: tsc: Add Airmont reference clock values Bin Meng
                   ` (12 more replies)
  0 siblings, 13 replies; 47+ messages in thread
From: Bin Meng @ 2017-08-16  5:41 UTC (permalink / raw
  To: u-boot

Intel Braswell SoC is the follow-up processor of BayTrail on the
Atom product line. This support utilizes Intel FSP firmware to
initialize the SoC. Note its FSP is spec 1.1 compliant, but it
is still backward compatible with spec 1.0. For simplicity, we
are using the spec 1.0 APIs to do the initialization.

There are 3 big differences from previous SoCs:
- No ICH6 legacy GPIO controller. FSP uses a custom table to
  configure the pin mux and pads.
- No legacy VGA BIOS is supplied. Instead a new type of binary
  called Intel Video BIOS Table (VBT) is used by FSP to initialize
  the integrated graphics device.
- No EHCI controller, only an xHCI controller integrated.

The support is validated on Intel Cherry Hill board, a board based
on Intel Braswell SoC.

This series is available at u-boot-x86/braswell-working.


Bin Meng (13):
  x86: tsc: Add Airmont reference clock values
  x86: fsp: Update struct common_buf for FSP spec 1.1
  x86: fsp: Add FSP_GRAPHICS_INFO_HOB
  x86: Add Video BIOS Table (VBT) related Kconfig options
  tools: binman: Add a new entry type for Intel VBT
  x86: dts: Include Intel Video BIOS Table in the ROM image
  x86: dm: video: Add a framebuffer driver that utilizes VBT
  x86: fsp: Update fsp command to show spec 1.1 header
  x86: Add Intel Braswell SoC support
  x86: braswell: Add microcode for B0/C0/D0 stepping SoC
  x86: braswell: Add FSP configuration
  x86: braswell: Disable PUNIT power configuration for B0 stepping
  x86: Support Intel Cherry Hill board

 arch/x86/Kconfig                                   |   43 +
 arch/x86/cpu/Makefile                              |    1 +
 arch/x86/cpu/braswell/Kconfig                      |   38 +
 arch/x86/cpu/braswell/Makefile                     |    7 +
 arch/x86/cpu/braswell/braswell.c                   |   36 +
 arch/x86/cpu/braswell/cpu.c                        |  170 +
 arch/x86/cpu/braswell/early_uart.c                 |   86 +
 arch/x86/cpu/braswell/fsp_configs.c                |  164 +
 arch/x86/dts/Makefile                              |    1 +
 arch/x86/dts/cherryhill.dts                        |  215 +
 arch/x86/dts/microcode/m01406c2220.dtsi            | 4308 ++++++++++++++++++++
 arch/x86/dts/microcode/m01406c3363.dtsi            | 4308 ++++++++++++++++++++
 arch/x86/dts/microcode/m01406c440a.dtsi            | 4308 ++++++++++++++++++++
 arch/x86/dts/u-boot.dtsi                           |    6 +
 .../include/asm/arch-braswell/fsp/fsp_configs.h    |   89 +
 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h   |  172 +
 arch/x86/include/asm/arch-braswell/gpio.h          |  234 ++
 arch/x86/include/asm/arch-braswell/iomap.h         |   50 +
 arch/x86/include/asm/fsp/fsp_api.h                 |    3 +-
 arch/x86/include/asm/fsp/fsp_hob.h                 |   34 +
 arch/x86/include/asm/fsp/fsp_infoheader.h          |    9 +-
 arch/x86/include/asm/fsp/fsp_support.h             |   12 +
 arch/x86/lib/fsp/Makefile                          |    1 +
 arch/x86/lib/fsp/cmd_fsp.c                         |   24 +-
 arch/x86/lib/fsp/fsp_graphics.c                    |  124 +
 arch/x86/lib/fsp/fsp_support.c                     |    7 +
 board/intel/Kconfig                                |   10 +
 board/intel/cherryhill/Kconfig                     |   25 +
 board/intel/cherryhill/MAINTAINERS                 |    6 +
 board/intel/cherryhill/Makefile                    |    7 +
 board/intel/cherryhill/cherryhill.c                |  596 +++
 board/intel/cherryhill/start.S                     |    9 +
 configs/cherryhill_defconfig                       |   36 +
 doc/README.x86                                     |   30 +
 drivers/timer/tsc_timer.c                          |   17 +-
 include/configs/cherryhill.h                       |   22 +
 tools/binman/etype/intel_vbt.py                    |   14 +
 tools/binman/func_test.py                          |    9 +-
 tools/binman/test/46_intel-vbt.dts                 |   14 +
 39 files changed, 15233 insertions(+), 12 deletions(-)
 create mode 100644 arch/x86/cpu/braswell/Kconfig
 create mode 100644 arch/x86/cpu/braswell/Makefile
 create mode 100644 arch/x86/cpu/braswell/braswell.c
 create mode 100644 arch/x86/cpu/braswell/cpu.c
 create mode 100644 arch/x86/cpu/braswell/early_uart.c
 create mode 100644 arch/x86/cpu/braswell/fsp_configs.c
 create mode 100644 arch/x86/dts/cherryhill.dts
 create mode 100644 arch/x86/dts/microcode/m01406c2220.dtsi
 create mode 100644 arch/x86/dts/microcode/m01406c3363.dtsi
 create mode 100644 arch/x86/dts/microcode/m01406c440a.dtsi
 create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
 create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
 create mode 100644 arch/x86/include/asm/arch-braswell/gpio.h
 create mode 100644 arch/x86/include/asm/arch-braswell/iomap.h
 create mode 100644 arch/x86/lib/fsp/fsp_graphics.c
 create mode 100644 board/intel/cherryhill/Kconfig
 create mode 100644 board/intel/cherryhill/MAINTAINERS
 create mode 100644 board/intel/cherryhill/Makefile
 create mode 100644 board/intel/cherryhill/cherryhill.c
 create mode 100644 board/intel/cherryhill/start.S
 create mode 100644 configs/cherryhill_defconfig
 create mode 100644 include/configs/cherryhill.h
 create mode 100644 tools/binman/etype/intel_vbt.py
 create mode 100644 tools/binman/test/46_intel-vbt.dts

-- 
2.9.2

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 01/13] x86: tsc: Add Airmont reference clock values
  2017-08-16  5:41 [U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support Bin Meng
@ 2017-08-16  5:41 ` Bin Meng
  2017-08-26 13:38   ` Simon Glass
  2017-08-16  5:41 ` [U-Boot] [PATCH 02/13] x86: fsp: Update struct common_buf for FSP spec 1.1 Bin Meng
                   ` (11 subsequent siblings)
  12 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-16  5:41 UTC (permalink / raw
  To: u-boot

Per the Intel 64 and IA-32 Architecture Software Developer's Manual,
add the reference clock for Intel Atom Processors based on the Airmont
Microarchitecture (Braswell).

This keeps in sync with Linux kernel commit:
  6fcb41c: x86/tsc_msr: Add Airmont reference clock values

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 drivers/timer/tsc_timer.c | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 4d1fc9c..77040af 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -18,7 +18,7 @@
 #include <asm/msr.h>
 #include <asm/u-boot-x86.h>
 
-#define MAX_NUM_FREQS	8
+#define MAX_NUM_FREQS	9
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -40,17 +40,20 @@ struct freq_desc {
 
 static struct freq_desc freq_desc_tables[] = {
 	/* PNW */
-	{ 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 } },
+	{ 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
 	/* CLV+ */
-	{ 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },
+	{ 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
 	/* TNG - Intel Atom processor Z3400 series */
-	{ 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },
+	{ 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
 	/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
-	{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },
+	{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
 	/* ANN - Intel Atom processor Z3500 series */
-	{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } },
+	{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
+	/* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
+	{ 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
+			80000, 93300, 90000, 88900, 87500 } },
 	/* Ivybridge */
-	{ 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
+	{ 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
 };
 
 static int match_cpu(u8 family, u8 model)
-- 
2.9.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 02/13] x86: fsp: Update struct common_buf for FSP spec 1.1
  2017-08-16  5:41 [U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support Bin Meng
  2017-08-16  5:41 ` [U-Boot] [PATCH 01/13] x86: tsc: Add Airmont reference clock values Bin Meng
@ 2017-08-16  5:41 ` Bin Meng
  2017-08-26 13:38   ` Simon Glass
  2017-08-16  5:41 ` [U-Boot] [PATCH 03/13] x86: fsp: Add FSP_GRAPHICS_INFO_HOB Bin Meng
                   ` (10 subsequent siblings)
  12 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-16  5:41 UTC (permalink / raw
  To: u-boot

FSP spec 1.1 adds one more member to the struct common_buf to
determine the memory size that can be reserved by FSP below "top
of low usable memory" for bootloader usage. This new member uses
the reserved space so that it is still compatible with previous
FSP spec 1.0.

A new HOB (FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID) is also
published when common_buf.tolum_size is valid and non zero.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/include/asm/fsp/fsp_api.h | 3 ++-
 arch/x86/include/asm/fsp/fsp_hob.h | 8 ++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h
index afafb30..43f0cdb 100644
--- a/arch/x86/include/asm/fsp/fsp_api.h
+++ b/arch/x86/include/asm/fsp/fsp_api.h
@@ -43,7 +43,8 @@ struct common_buf {
 	u32	stack_top;
 	u32	boot_mode;	/* Current system boot mode */
 	void	*upd_data;	/* User platform configuraiton data region */
-	u32	reserved[7];	/* Reserved */
+	u32	tolum_size;	/* Top of low usable memory size (FSP 1.1) */
+	u32	reserved[6];	/* Reserved */
 };
 
 enum fsp_phase {
diff --git a/arch/x86/include/asm/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h
index 7c22bcd..8ce665e 100644
--- a/arch/x86/include/asm/fsp/fsp_hob.h
+++ b/arch/x86/include/asm/fsp/fsp_hob.h
@@ -242,4 +242,12 @@ static inline u16 get_guid_hob_data_size(const struct hob_header *hdr)
 	{ 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \
 	}
 
+/* The following GUIDs are newly introduced in FSP spec 1.1 */
+
+#define FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID \
+	{ \
+	0x73ff4f56, 0xaa8e, 0x4451, \
+	{ 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } \
+	}
+
 #endif
-- 
2.9.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 03/13] x86: fsp: Add FSP_GRAPHICS_INFO_HOB
  2017-08-16  5:41 [U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support Bin Meng
  2017-08-16  5:41 ` [U-Boot] [PATCH 01/13] x86: tsc: Add Airmont reference clock values Bin Meng
  2017-08-16  5:41 ` [U-Boot] [PATCH 02/13] x86: fsp: Update struct common_buf for FSP spec 1.1 Bin Meng
@ 2017-08-16  5:41 ` Bin Meng
  2017-08-26 13:38   ` Simon Glass
  2017-08-16  5:41 ` [U-Boot] [PATCH 04/13] x86: Add Video BIOS Table (VBT) related Kconfig options Bin Meng
                   ` (9 subsequent siblings)
  12 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-16  5:41 UTC (permalink / raw
  To: u-boot

This adds a new HOB type for graphics information introduced in FSP
spec 1.1. When graphics capability is included in FSP and enabled,
FSP produces an FSP_GRAPHICS_INFO_HOB as described in the EFI PI
specification which provides information about the graphics mode and
framebuffer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/include/asm/fsp/fsp_hob.h     | 26 ++++++++++++++++++++++++++
 arch/x86/include/asm/fsp/fsp_support.h | 12 ++++++++++++
 arch/x86/lib/fsp/fsp_support.c         |  7 +++++++
 3 files changed, 45 insertions(+)

diff --git a/arch/x86/include/asm/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h
index 8ce665e..244f86e 100644
--- a/arch/x86/include/asm/fsp/fsp_hob.h
+++ b/arch/x86/include/asm/fsp/fsp_hob.h
@@ -127,6 +127,26 @@ struct hob_guid {
 	/* GUID specific data goes here */
 };
 
+enum pixel_format {
+	pixel_rgbx_8bpc,	/* RGB 8 bit per color */
+	pixel_bgrx_8bpc,	/* BGR 8 bit per color */
+	pixel_bitmask,
+};
+
+struct __packed hob_graphics_info {
+	phys_addr_t fb_base;	/* framebuffer base address */
+	u32 fb_size;		/* framebuffer size */
+	u32 version;
+	u32 width;
+	u32 height;
+	enum pixel_format pixel_format;
+	u32 red_mask;
+	u32 green_mask;
+	u32 blue_mask;
+	u32 reserved_mask;
+	u32 pixels_per_scanline;
+};
+
 /**
  * get_next_hob() - return a pointer to the next HOB in the HOB list
  *
@@ -250,4 +270,10 @@ static inline u16 get_guid_hob_data_size(const struct hob_header *hdr)
 	{ 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } \
 	}
 
+#define FSP_GRAPHICS_INFO_HOB_GUID \
+	{ \
+	0x39f62cce, 0x6825, 0x4669, \
+	{ 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 } \
+	}
+
 #endif
diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h
index 61d811f..97a50b0 100644
--- a/arch/x86/include/asm/fsp/fsp_support.h
+++ b/arch/x86/include/asm/fsp/fsp_support.h
@@ -191,6 +191,18 @@ void *fsp_get_nvs_data(const void *hob_list, u32 *len);
 void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);
 
 /**
+ * This function retrieves graphics information.
+ *
+ * @hob_list:      A HOB list pointer.
+ * @len:           A pointer to the graphics info HOB length.
+ *                 If the HOB is located, the length will be updated.
+ *
+ * @retval NULL:   Failed to find the graphics info HOB.
+ * @retval others: A pointer to struct hob_graphics_info.
+ */
+void *fsp_get_graphics_info(const void *hob_list, u32 *len);
+
+/**
  * This function overrides the default configurations of FSP.
  *
  * @config:  A pointer to the FSP configuration data structure
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index ab8340c..e0c49be 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -425,3 +425,10 @@ void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len)
 
 	return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
 }
+
+void *fsp_get_graphics_info(const void *hob_list, u32 *len)
+{
+	const struct efi_guid guid = FSP_GRAPHICS_INFO_HOB_GUID;
+
+	return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
+}
-- 
2.9.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 04/13] x86: Add Video BIOS Table (VBT) related Kconfig options
  2017-08-16  5:41 [U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support Bin Meng
                   ` (2 preceding siblings ...)
  2017-08-16  5:41 ` [U-Boot] [PATCH 03/13] x86: fsp: Add FSP_GRAPHICS_INFO_HOB Bin Meng
@ 2017-08-16  5:41 ` Bin Meng
  2017-08-26 13:38   ` Simon Glass
  2017-08-16  5:41 ` [U-Boot] [PATCH 05/13] tools: binman: Add a new entry type for Intel VBT Bin Meng
                   ` (8 subsequent siblings)
  12 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-16  5:41 UTC (permalink / raw
  To: u-boot

This adds Kconfig options for Video BIOS Table which is normally
required if you are using an Intel FSP firmware that is complaint
with spec 1.1 or later to initialize the integrated graphics device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/Kconfig | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5373082..b0d3266 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -551,6 +551,40 @@ config VGA_BIOS_ADDR
 	  address of 0xfff90000 indicates that the image will be put at offset
 	  0x90000 from the beginning of a 1MB flash device.
 
+config HAVE_VBT
+	bool "Add a Video BIOS Table (VBT) image"
+	depends on HAVE_FSP
+	help
+	  Select this option if you have a Video BIOS Table (VBT) image that
+	  you would like to add to your ROM. This is normally required if you
+	  are using an Intel FSP firmware that is complaint with spec 1.1 or
+	  later to initialize the integrated graphics device (IGD).
+
+	  Video BIOS Table, or VBT, provides platform and board specific
+	  configuration information to the driver that is not discoverable
+	  or available through other means. By other means the most used
+	  method here is to read EDID table from the attached monitor, over
+	  Display Data Channel (DDC) using two pin I2C serial interface. VBT
+	  configuration is related to display hardware and is available via
+	  the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
+
+config VBT_FILE
+	string "Video BIOS Table (VBT) image filename"
+	depends on HAVE_VBT
+	default "vbt.bin"
+	help
+	  The filename of the file to use as Video BIOS Table (VBT) image
+	  in the board directory.
+
+config VBT_ADDR
+	hex "Video BIOS Table (VBT) image location"
+	depends on HAVE_VBT
+	default 0xfff90000
+	help
+	  The location of Video BIOS Table (VBT) image in the SPI flash. For
+	  example, base address of 0xfff90000 indicates that the image will
+	  be put at offset 0x90000 from the beginning of a 1MB flash device.
+
 config ROM_TABLE_ADDR
 	hex
 	default 0xf0000
-- 
2.9.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 05/13] tools: binman: Add a new entry type for Intel VBT
  2017-08-16  5:41 [U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support Bin Meng
                   ` (3 preceding siblings ...)
  2017-08-16  5:41 ` [U-Boot] [PATCH 04/13] x86: Add Video BIOS Table (VBT) related Kconfig options Bin Meng
@ 2017-08-16  5:41 ` Bin Meng
  2017-08-26 13:38   ` Simon Glass
  2017-08-16  5:41 ` [U-Boot] [PATCH 06/13] x86: dts: Include Intel Video BIOS Table in the ROM image Bin Meng
                   ` (7 subsequent siblings)
  12 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-16  5:41 UTC (permalink / raw
  To: u-boot

This adds a new entry type for Intel Video BIOS Table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 tools/binman/etype/intel_vbt.py    | 14 ++++++++++++++
 tools/binman/func_test.py          |  9 ++++++++-
 tools/binman/test/46_intel-vbt.dts | 14 ++++++++++++++
 3 files changed, 36 insertions(+), 1 deletion(-)
 create mode 100644 tools/binman/etype/intel_vbt.py
 create mode 100644 tools/binman/test/46_intel-vbt.dts

diff --git a/tools/binman/etype/intel_vbt.py b/tools/binman/etype/intel_vbt.py
new file mode 100644
index 0000000..29aedaf
--- /dev/null
+++ b/tools/binman/etype/intel_vbt.py
@@ -0,0 +1,14 @@
+#
+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Entry-type module for Intel Video BIOS Table binary blob
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_intel_vbt(Entry_blob):
+    def __init__(self, image, etype, node):
+        Entry_blob.__init__(self, image, etype, node)
diff --git a/tools/binman/func_test.py b/tools/binman/func_test.py
index 8b4db41..c4207ce 100644
--- a/tools/binman/func_test.py
+++ b/tools/binman/func_test.py
@@ -38,6 +38,7 @@ X86_START16_DATA    = 'start16'
 U_BOOT_NODTB_DATA   = 'nodtb with microcode pointer somewhere in here'
 FSP_DATA            = 'fsp'
 CMC_DATA            = 'cmc'
+VBT_DATA            = 'vbt'
 
 class TestFunctional(unittest.TestCase):
     """Functional tests for binman
@@ -74,6 +75,7 @@ class TestFunctional(unittest.TestCase):
         TestFunctional._MakeInputFile('u-boot-nodtb.bin', U_BOOT_NODTB_DATA)
         TestFunctional._MakeInputFile('fsp.bin', FSP_DATA)
         TestFunctional._MakeInputFile('cmc.bin', CMC_DATA)
+        TestFunctional._MakeInputFile('vbt.bin', VBT_DATA)
         self._output_setup = False
 
         # ELF file with a '_dt_ucode_base_size' symbol
@@ -801,6 +803,11 @@ class TestFunctional(unittest.TestCase):
         self.assertEqual(FSP_DATA, data[:len(FSP_DATA)])
 
     def testPackCmc(self):
-        """Test that an image with a FSP binary can be created"""
+        """Test that an image with a CMC binary can be created"""
         data = self._DoReadFile('43_intel-cmc.dts')
         self.assertEqual(CMC_DATA, data[:len(CMC_DATA)])
+
+    def testPackVbt(self):
+        """Test that an image with a VBT binary can be created"""
+        data = self._DoReadFile('46_intel-vbt.dts')
+        self.assertEqual(VBT_DATA, data[:len(VBT_DATA)])
diff --git a/tools/binman/test/46_intel-vbt.dts b/tools/binman/test/46_intel-vbt.dts
new file mode 100644
index 0000000..733f575
--- /dev/null
+++ b/tools/binman/test/46_intel-vbt.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		size = <16>;
+
+		intel-vbt {
+			filename = "vbt.bin";
+		};
+	};
+};
-- 
2.9.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 06/13] x86: dts: Include Intel Video BIOS Table in the ROM image
  2017-08-16  5:41 [U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support Bin Meng
                   ` (4 preceding siblings ...)
  2017-08-16  5:41 ` [U-Boot] [PATCH 05/13] tools: binman: Add a new entry type for Intel VBT Bin Meng
@ 2017-08-16  5:41 ` Bin Meng
  2017-08-26 13:39   ` Simon Glass
  2017-08-16  5:41 ` [U-Boot] [PATCH 07/13] x86: dm: video: Add a framebuffer driver that utilizes VBT Bin Meng
                   ` (6 subsequent siblings)
  12 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-16  5:41 UTC (permalink / raw
  To: u-boot

Now that binman is able to recognize the Video BIOS Table entry,
add such one in the u-boot.dtsi.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/dts/u-boot.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index a4321d3..7e37d4f 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -67,6 +67,12 @@
 			pos = <CONFIG_VGA_BIOS_ADDR>;
 		};
 #endif
+#ifdef CONFIG_HAVE_VBT
+		intel-vbt {
+			filename = CONFIG_VBT_FILE;
+			pos = <CONFIG_VBT_ADDR>;
+		};
+#endif
 #ifdef CONFIG_HAVE_REFCODE
 		intel-refcode {
 			pos = <CONFIG_X86_REFCODE_ADDR>;
-- 
2.9.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 07/13] x86: dm: video: Add a framebuffer driver that utilizes VBT
  2017-08-16  5:41 [U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support Bin Meng
                   ` (5 preceding siblings ...)
  2017-08-16  5:41 ` [U-Boot] [PATCH 06/13] x86: dts: Include Intel Video BIOS Table in the ROM image Bin Meng
@ 2017-08-16  5:41 ` Bin Meng
  2017-08-26  3:36   ` Simon Glass
  2017-08-16  5:41 ` [U-Boot] [PATCH 08/13] x86: fsp: Update fsp command to show spec 1.1 header Bin Meng
                   ` (5 subsequent siblings)
  12 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-16  5:41 UTC (permalink / raw
  To: u-boot

When a VBT is given to an FSP that supports graphics initialization,
the FSP will produce a graphics info HOB that contains all necessary
information for the linear frame buffer of the integrated graphics
device. This adds a DM video driver for it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/Kconfig                |   8 +++
 arch/x86/lib/fsp/Makefile       |   1 +
 arch/x86/lib/fsp/fsp_graphics.c | 124 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 133 insertions(+)
 create mode 100644 arch/x86/lib/fsp/fsp_graphics.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index b0d3266..f72d307 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -585,6 +585,14 @@ config VBT_ADDR
 	  example, base address of 0xfff90000 indicates that the image will
 	  be put at offset 0x90000 from the beginning of a 1MB flash device.
 
+config VIDEO_FSP
+	bool "Enable FSP framebuffer driver support"
+	depends on HAVE_VBT && DM_VIDEO
+	help
+	  Turn on this option to enable a framebuffer driver when U-Boot is
+	  using Video BIOS Table (VBT) image for FSP firmware to initialize
+	  the integrated graphics device.
+
 config ROM_TABLE_ADDR
 	hex
 	default 0xf0000
diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
index 3ea4880..afe83dd3 100644
--- a/arch/x86/lib/fsp/Makefile
+++ b/arch/x86/lib/fsp/Makefile
@@ -8,4 +8,5 @@ obj-y += cmd_fsp.o
 obj-y += fsp_car.o
 obj-y += fsp_common.o
 obj-y += fsp_dram.o
+obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o
 obj-y += fsp_support.o
diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c
new file mode 100644
index 0000000..a19b067
--- /dev/null
+++ b/arch/x86/lib/fsp/fsp_graphics.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <vbe.h>
+#include <video.h>
+#include <asm/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pixel {
+	u8 pos;
+	u8 size;
+};
+
+static const struct fsp_framebuffer {
+	struct pixel red;
+	struct pixel green;
+	struct pixel blue;
+	struct pixel rsvd;
+} fsp_framebuffer_format_map[] = {
+	[pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} },
+	[pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
+};
+
+static int save_vesa_mode(struct vesa_mode_info *vesa)
+{
+	const struct hob_graphics_info *ginfo;
+	const struct fsp_framebuffer *fbinfo;
+
+	ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL);
+
+	/*
+	 * If there is no graphics info structure, bail out and keep
+	 * running on the serial console.
+	 */
+	if (!ginfo) {
+		debug("FSP graphics hand-off block not found\n");
+		return -ENXIO;
+	}
+
+	vesa->x_resolution = ginfo->width;
+	vesa->y_resolution = ginfo->height;
+	vesa->bits_per_pixel = 32;
+	vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4;
+	vesa->phys_base_ptr = ginfo->fb_base;
+
+	if (ginfo->pixel_format >= pixel_bitmask) {
+		debug("FSP set unknown framebuffer format: %d\n",
+		      ginfo->pixel_format);
+		return -EINVAL;
+	}
+	fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format];
+	vesa->red_mask_size = fbinfo->red.size;
+	vesa->red_mask_pos = fbinfo->red.pos;
+	vesa->green_mask_size = fbinfo->green.size;
+	vesa->green_mask_pos = fbinfo->green.pos;
+	vesa->blue_mask_size = fbinfo->blue.size;
+	vesa->blue_mask_pos = fbinfo->blue.pos;
+	vesa->reserved_mask_size = fbinfo->rsvd.size;
+	vesa->reserved_mask_pos = fbinfo->rsvd.pos;
+
+	return 0;
+}
+
+static int fsp_video_probe(struct udevice *dev)
+{
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct vesa_mode_info *vesa = &mode_info.vesa;
+	int ret;
+
+	printf("Video: ");
+
+	/* Initialize vesa_mode_info structure */
+	ret = save_vesa_mode(vesa);
+	if (ret)
+		goto err;
+
+	/*
+	 * The framebuffer base address in the FSP graphics info HOB reflects
+	 * the value assigned by the FSP. After PCI enumeration the framebuffer
+	 * base address may be relocated. Let's get the updated one from device.
+	 *
+	 * For IGD, it seems to be always on BAR2.
+	 */
+	vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
+
+	ret = vbe_setup_video_priv(vesa, uc_priv, plat);
+	if (ret)
+		goto err;
+
+	printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
+	       vesa->bits_per_pixel);
+
+	return 0;
+
+err:
+	printf("No video mode configured in FSP!\n");
+	return ret;
+}
+
+static const struct udevice_id fsp_video_ids[] = {
+	{ .compatible = "fsp-fb" },
+	{ }
+};
+
+U_BOOT_DRIVER(fsp_video) = {
+	.name	= "fsp_video",
+	.id	= UCLASS_VIDEO,
+	.of_match = fsp_video_ids,
+	.probe	= fsp_video_probe,
+};
+
+static struct pci_device_id fsp_video_supported[] = {
+	{ PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) },
+	{ },
+};
+
+U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported);
-- 
2.9.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 08/13] x86: fsp: Update fsp command to show spec 1.1 header
  2017-08-16  5:41 [U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support Bin Meng
                   ` (6 preceding siblings ...)
  2017-08-16  5:41 ` [U-Boot] [PATCH 07/13] x86: dm: video: Add a framebuffer driver that utilizes VBT Bin Meng
@ 2017-08-16  5:41 ` Bin Meng
  2017-08-26 13:39   ` Simon Glass
  2017-08-16  5:41 ` [U-Boot] [PATCH 09/13] x86: Add Intel Braswell SoC support Bin Meng
                   ` (4 subsequent siblings)
  12 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-16  5:41 UTC (permalink / raw
  To: u-boot

FSP spec 1.1 adds 3 new APIs and their offsets are in the header.
Update the 'fsp hdr' command to show these new entries.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/include/asm/fsp/fsp_infoheader.h |  9 ++++++++-
 arch/x86/lib/fsp/cmd_fsp.c                | 24 ++++++++++++++++++++++--
 2 files changed, 30 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/fsp/fsp_infoheader.h b/arch/x86/include/asm/fsp/fsp_infoheader.h
index 4a4d627..60ce61d 100644
--- a/arch/x86/include/asm/fsp/fsp_infoheader.h
+++ b/arch/x86/include/asm/fsp/fsp_infoheader.h
@@ -26,7 +26,14 @@ struct __packed fsp_header {
 	u32	fsp_tempram_init;	/* tempram_init offset */
 	u32	fsp_init;		/* fsp_init offset */
 	u32	fsp_notify;		/* fsp_notify offset */
-	u32	reserved2;
+	u32	fsp_mem_init;		/* fsp_mem_init offset */
+	u32	fsp_tempram_exit;	/* fsp_tempram_exit offset */
+	u32	fsp_silicon_init;	/* fsp_silicon_init offset */
 };
 
+#define FSP_HEADER_REVISION_1		1
+#define FSP_HEADER_REVISION_2		2
+
+#define FSP_ATTR_GRAPHICS_SUPPORT	(1 << 0)
+
 #endif
diff --git a/arch/x86/lib/fsp/cmd_fsp.c b/arch/x86/lib/fsp/cmd_fsp.c
index 2554663..2a99cfe 100644
--- a/arch/x86/lib/fsp/cmd_fsp.c
+++ b/arch/x86/lib/fsp/cmd_fsp.c
@@ -38,17 +38,37 @@ static int do_hdr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	for (i = 0; i < sizeof(hdr->sign); i++)
 		printf("%c", *sign++);
 	printf(", size %d, rev %d\n", hdr->hdr_len, hdr->hdr_rev);
-	printf("Image  : rev %d.%d, id ",
-	       (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff);
+	printf("Image  : rev ");
+	if (hdr->hdr_rev == FSP_HEADER_REVISION_1) {
+		printf("%d.%d",
+		       (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff);
+	} else {
+		printf("%d.%d.%d.%d",
+		       (hdr->img_rev >> 24) & 0xff, (hdr->img_rev >> 16) & 0xff,
+		       (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff);
+	}
+	printf(", id ");
 	for (i = 0; i < ARRAY_SIZE(hdr->img_id); i++)
 		printf("%c", hdr->img_id[i]);
 	printf(", addr 0x%08x, size %d\n", img_addr, hdr->img_size);
+	if (hdr->hdr_rev == FSP_HEADER_REVISION_2) {
+		printf("GFX    :%ssupported\n",
+		       hdr->img_attr & FSP_ATTR_GRAPHICS_SUPPORT ? " " : " un");
+	}
 	printf("VPD    : addr 0x%08x, size %d\n",
 	       hdr->cfg_region_off + img_addr, hdr->cfg_region_size);
 	printf("\nNumber of APIs Supported : %d\n", hdr->api_num);
 	printf("\tTempRamInit : 0x%08x\n", hdr->fsp_tempram_init + img_addr);
 	printf("\tFspInit     : 0x%08x\n", hdr->fsp_init + img_addr);
 	printf("\tFspNotify   : 0x%08x\n", hdr->fsp_notify + img_addr);
+	if (hdr->hdr_rev == FSP_HEADER_REVISION_2) {
+		printf("\tMemoryInit  : 0x%08x\n",
+		       hdr->fsp_mem_init + img_addr);
+		printf("\tTempRamExit : 0x%08x\n",
+		       hdr->fsp_tempram_exit + img_addr);
+		printf("\tSiliconInit : 0x%08x\n",
+		       hdr->fsp_silicon_init + img_addr);
+	}
 
 	return 0;
 }
-- 
2.9.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 09/13] x86: Add Intel Braswell SoC support
  2017-08-16  5:41 [U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support Bin Meng
                   ` (7 preceding siblings ...)
  2017-08-16  5:41 ` [U-Boot] [PATCH 08/13] x86: fsp: Update fsp command to show spec 1.1 header Bin Meng
@ 2017-08-16  5:41 ` Bin Meng
  2017-08-26 13:39   ` Simon Glass
  2017-08-16  5:41 ` [U-Boot] [PATCH 10/13] x86: braswell: Add microcode for B0/C0/D0 stepping SoC Bin Meng
                   ` (3 subsequent siblings)
  12 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-16  5:41 UTC (permalink / raw
  To: u-boot

This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.

Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/Kconfig                           |   1 +
 arch/x86/cpu/Makefile                      |   1 +
 arch/x86/cpu/braswell/Kconfig              |  38 +++++++
 arch/x86/cpu/braswell/Makefile             |   7 ++
 arch/x86/cpu/braswell/braswell.c           |  36 ++++++
 arch/x86/cpu/braswell/cpu.c                | 170 +++++++++++++++++++++++++++++
 arch/x86/cpu/braswell/early_uart.c         |  86 +++++++++++++++
 arch/x86/include/asm/arch-braswell/iomap.h |  50 +++++++++
 8 files changed, 389 insertions(+)
 create mode 100644 arch/x86/cpu/braswell/Kconfig
 create mode 100644 arch/x86/cpu/braswell/Makefile
 create mode 100644 arch/x86/cpu/braswell/braswell.c
 create mode 100644 arch/x86/cpu/braswell/cpu.c
 create mode 100644 arch/x86/cpu/braswell/early_uart.c
 create mode 100644 arch/x86/include/asm/arch-braswell/iomap.h

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index f72d307..9620764 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -108,6 +108,7 @@ source "board/intel/Kconfig"
 
 # platform-specific options below
 source "arch/x86/cpu/baytrail/Kconfig"
+source "arch/x86/cpu/braswell/Kconfig"
 source "arch/x86/cpu/broadwell/Kconfig"
 source "arch/x86/cpu/coreboot/Kconfig"
 source "arch/x86/cpu/ivybridge/Kconfig"
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 999429e..94cdff1 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -27,6 +27,7 @@ endif
 
 obj-y += intel_common/
 obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
+obj-$(CONFIG_INTEL_BRASWELL) += braswell/
 obj-$(CONFIG_INTEL_BROADWELL) += broadwell/
 obj-$(CONFIG_SYS_COREBOOT) += coreboot/
 obj-$(CONFIG_EFI_APP) += efi/
diff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig
new file mode 100644
index 0000000..c993889
--- /dev/null
+++ b/arch/x86/cpu/braswell/Kconfig
@@ -0,0 +1,38 @@
+#
+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+config INTEL_BRASWELL
+	bool
+	select HAVE_FSP
+	select ARCH_MISC_INIT
+	imply HAVE_INTEL_ME
+	imply HAVE_VBT
+	imply ENABLE_MRC_CACHE
+	imply ENV_IS_IN_SPI_FLASH
+	imply AHCI_PCI
+	imply ICH_SPI
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply SCSI
+	imply SPI_FLASH
+	imply SYS_NS16550
+	imply USB
+	imply USB_XHCI_HCD
+	imply VIDEO_FSP
+
+if INTEL_BRASWELL
+
+config FSP_ADDR
+	hex
+	default 0xfff20000
+
+config FSP_LOCKDOWN_SPI
+	bool
+	default y
+
+endif
diff --git a/arch/x86/cpu/braswell/Makefile b/arch/x86/cpu/braswell/Makefile
new file mode 100644
index 0000000..19bcee6
--- /dev/null
+++ b/arch/x86/cpu/braswell/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += braswell.o cpu.o early_uart.o
diff --git a/arch/x86/cpu/braswell/braswell.c b/arch/x86/cpu/braswell/braswell.c
new file mode 100644
index 0000000..37099aa
--- /dev/null
+++ b/arch/x86/cpu/braswell/braswell.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mrccache.h>
+#include <asm/post.h>
+
+int arch_cpu_init(void)
+{
+	post_code(POST_CPU_INIT);
+
+	return x86_cpu_init_f();
+}
+
+int arch_misc_init(void)
+{
+#ifdef CONFIG_ENABLE_MRC_CACHE
+	/*
+	 * We intend not to check any return value here, as even MRC cache
+	 * is not saved successfully, it is not a severe error that will
+	 * prevent system from continuing to boot.
+	 */
+	mrccache_save();
+#endif
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	/* cold reset */
+	x86_full_reset();
+}
diff --git a/arch/x86/cpu/braswell/cpu.c b/arch/x86/cpu/braswell/cpu.c
new file mode 100644
index 0000000..6ff9036
--- /dev/null
+++ b/arch/x86/cpu/braswell/cpu.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Derived from arch/x86/cpu/baytrail/cpu.c
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <asm/cpu.h>
+#include <asm/cpu_x86.h>
+#include <asm/io.h>
+#include <asm/lapic.h>
+#include <asm/msr.h>
+#include <asm/turbo.h>
+
+static const unsigned int braswell_bus_freq_table[] = {
+	83333333,
+	100000000,
+	133333333,
+	116666666,
+	80000000,
+	93333333,
+	90000000,
+	88900000,
+	87500000
+};
+
+static unsigned int braswell_bus_freq(void)
+{
+	msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
+
+	if ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table)))
+		return braswell_bus_freq_table[clk_info.lo & 0xf];
+
+	return 0;
+}
+
+static unsigned long braswell_tsc_freq(void)
+{
+	msr_t platform_info;
+	ulong bclk = braswell_bus_freq();
+
+	if (!bclk)
+		return 0;
+
+	platform_info = msr_read(MSR_PLATFORM_INFO);
+
+	return bclk * ((platform_info.lo >> 8) & 0xff);
+}
+
+static int braswell_get_info(struct udevice *dev, struct cpu_info *info)
+{
+	info->cpu_freq = braswell_tsc_freq();
+	info->features = (1 << CPU_FEAT_L1_CACHE) | (1 << CPU_FEAT_MMU);
+
+	return 0;
+}
+
+static int braswell_get_count(struct udevice *dev)
+{
+	int ecx = 0;
+
+	/*
+	 * Use the algorithm described in Intel 64 and IA-32 Architectures
+	 * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
+	 * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
+	 * of CPUID Extended Topology Leaf.
+	 */
+	while (1) {
+		struct cpuid_result leaf_b;
+
+		leaf_b = cpuid_ext(0xb, ecx);
+
+		/*
+		 * Braswell doesn't have hyperthreading so just determine the
+		 * number of cores by from level type (ecx[15:8] == * 2)
+		 */
+		if ((leaf_b.ecx & 0xff00) == 0x0200)
+			return leaf_b.ebx & 0xffff;
+
+		ecx++;
+	}
+
+	return 0;
+}
+
+static void braswell_set_max_freq(void)
+{
+	msr_t perf_ctl;
+	msr_t msr;
+
+	/* Enable speed step */
+	msr = msr_read(MSR_IA32_MISC_ENABLES);
+	msr.lo |= (1 << 16);
+	msr_write(MSR_IA32_MISC_ENABLES, msr);
+
+	/* Enable Burst Mode */
+	msr = msr_read(MSR_IA32_MISC_ENABLES);
+	msr.hi = 0;
+	msr_write(MSR_IA32_MISC_ENABLES, msr);
+
+	/*
+	 * Set guaranteed ratio [21:16] from IACORE_TURBO_RATIOS to
+	 * bits [15:8] of the PERF_CTL
+	 */
+	msr = msr_read(MSR_IACORE_TURBO_RATIOS);
+	perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
+
+	/*
+	 * Set guaranteed vid [22:16] from IACORE_TURBO_VIDS to
+	 * bits [7:0] of the PERF_CTL
+	 */
+	msr = msr_read(MSR_IACORE_TURBO_VIDS);
+	perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
+
+	perf_ctl.hi = 0;
+	msr_write(MSR_IA32_PERF_CTL, perf_ctl);
+}
+
+static int braswell_probe(struct udevice *dev)
+{
+	debug("Init Braswell core\n");
+
+	/*
+	 * On Braswell the turbo disable bit is actually scoped at the
+	 * building-block level, not package. For non-BSP cores that are
+	 * within a building block, enable turbo. The cores within the BSP's
+	 * building block will just see it already enabled and move on.
+	 */
+	if (lapicid())
+		turbo_enable();
+
+	/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
+	msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f080f, 0xe0008),
+	msr_clrsetbits_64(MSR_POWER_MISC,
+			  ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK, 0);
+
+	/* Disable C1E */
+	msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);
+	msr_setbits_64(MSR_POWER_MISC, 0x44);
+
+	/* Set this core to max frequency ratio */
+	braswell_set_max_freq();
+
+	return 0;
+}
+
+static const struct udevice_id braswell_ids[] = {
+	{ .compatible = "intel,braswell-cpu" },
+	{ }
+};
+
+static const struct cpu_ops braswell_ops = {
+	.get_desc	= cpu_x86_get_desc,
+	.get_info	= braswell_get_info,
+	.get_count	= braswell_get_count,
+	.get_vendor	= cpu_x86_get_vendor,
+};
+
+U_BOOT_DRIVER(cpu_x86_braswell_drv) = {
+	.name		= "cpu_x86_braswell",
+	.id		= UCLASS_CPU,
+	.of_match	= braswell_ids,
+	.bind		= cpu_x86_bind,
+	.probe		= braswell_probe,
+	.ops		= &braswell_ops,
+};
diff --git a/arch/x86/cpu/braswell/early_uart.c b/arch/x86/cpu/braswell/early_uart.c
new file mode 100644
index 0000000..0300e13
--- /dev/null
+++ b/arch/x86/cpu/braswell/early_uart.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define PCI_DEV_CONFIG(segbus, dev, fn) ( \
+		(((segbus) & 0xfff) << 20) | \
+		(((dev) & 0x1f) << 15) | \
+		(((fn)  & 0x07) << 12))
+
+/* Platform Controller Unit */
+#define LPC_DEV			0x1f
+#define LPC_FUNC		0
+
+/* Enable UART */
+#define UART_CONT		0x80
+
+/* UART PAD definitions */
+#define UART_RXD_COMMUITY	1
+#define UART_TXD_COMMUITY	1
+#define UART_RXD_FAMILY		4
+#define UART_TXD_FAMILY		4
+#define UART_RXD_PAD		2
+#define UART_TXD_PAD		7
+#define UART_RXD_FUNC		3
+#define UART_TXD_FUNC		3
+
+/* IO Memory */
+#define IO_BASE_ADDRESS		0xfed80000
+
+static inline uint32_t gpio_pconf0(int community, int family, int pad)
+{
+	return IO_BASE_ADDRESS + community * 0x8000 + 0x4400 +
+		family * 0x400 + pad * 8;
+}
+
+static void gpio_select_func(int community, int family, int pad, int func)
+{
+	uint32_t reg;
+	uint32_t pconf0_addr = gpio_pconf0(community, family, pad);
+
+	reg = readl(pconf0_addr);
+	reg &= ~(0xf << 16);
+	reg |= (func << 16);
+	writel(reg, pconf0_addr);
+}
+
+static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
+{
+	unsigned long addr;
+
+	addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
+	writel(value, addr);
+}
+
+/* This can be called after memory-mapped PCI is working */
+int setup_internal_uart(int enable)
+{
+	/* Enable or disable the legacy UART hardware */
+	x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
+			       enable);
+
+	/* All done for the disable part, so just return */
+	if (!enable)
+		return 0;
+
+	/*
+	 * Set up the pads to the UART function. This allows the signals to
+	 * leave the chip
+	 */
+	gpio_select_func(UART_RXD_COMMUITY, UART_RXD_FAMILY,
+			 UART_RXD_PAD, UART_RXD_FUNC);
+	gpio_select_func(UART_TXD_COMMUITY, UART_TXD_FAMILY,
+			 UART_TXD_PAD, UART_TXD_FUNC);
+
+	return 0;
+}
+
+void board_debug_uart_init(void)
+{
+	setup_internal_uart(1);
+}
diff --git a/arch/x86/include/asm/arch-braswell/iomap.h b/arch/x86/include/asm/arch-braswell/iomap.h
new file mode 100644
index 0000000..7df2dc5
--- /dev/null
+++ b/arch/x86/include/asm/arch-braswell/iomap.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BRASWELL_IOMAP_H_
+#define _BRASWELL_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* Power Management Controller */
+#define PMC_BASE_ADDRESS	0xfed03000
+#define PMC_BASE_SIZE		0x400
+
+/* Power Management Unit */
+#define PUNIT_BASE_ADDRESS	0xfed05000
+#define PUNIT_BASE_SIZE		0x800
+
+/* Intel Legacy Block */
+#define ILB_BASE_ADDRESS	0xfed08000
+#define ILB_BASE_SIZE		0x400
+
+/* SPI Bus */
+#define SPI_BASE_ADDRESS	0xfed01000
+#define SPI_BASE_SIZE		0x400
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS	0xfed1c000
+#define RCBA_BASE_SIZE		0x400
+
+/* IO Memory */
+#define IO_BASE_ADDRESS		0xfed80000
+#define IO_BASE_SIZE		0x4000
+
+/* MODPHY */
+#define MPHY_BASE_ADDRESS	0xfef00000
+#define MPHY_BASE_SIZE		0x100000
+
+/* IO Port bases */
+
+#define ACPI_BASE_ADDRESS	0x400
+#define ACPI_BASE_SIZE		0x80
+
+#define GPIO_BASE_ADDRESS	0x500
+#define GPIO_BASE_SIZE		0x100
+
+#define SMBUS_BASE_ADDRESS	0xefa0
+
+#endif /* _BRASWELL_IOMAP_H_ */
-- 
2.9.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 10/13] x86: braswell: Add microcode for B0/C0/D0 stepping SoC
  2017-08-16  5:41 [U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support Bin Meng
                   ` (8 preceding siblings ...)
  2017-08-16  5:41 ` [U-Boot] [PATCH 09/13] x86: Add Intel Braswell SoC support Bin Meng
@ 2017-08-16  5:41 ` Bin Meng
  2017-08-26 13:39   ` Simon Glass
  2017-08-16  5:42 ` [U-Boot] [PATCH 11/13] x86: braswell: Add FSP configuration Bin Meng
                   ` (2 subsequent siblings)
  12 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-16  5:41 UTC (permalink / raw
  To: u-boot

This adds microcode device tree fragment for Braswell B0 (406C2),
C0 (406C3) and D0 (406C4) stepping SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/dts/microcode/m01406c2220.dtsi | 4308 +++++++++++++++++++++++++++++++
 arch/x86/dts/microcode/m01406c3363.dtsi | 4308 +++++++++++++++++++++++++++++++
 arch/x86/dts/microcode/m01406c440a.dtsi | 4308 +++++++++++++++++++++++++++++++
 3 files changed, 12924 insertions(+)
 create mode 100644 arch/x86/dts/microcode/m01406c2220.dtsi
 create mode 100644 arch/x86/dts/microcode/m01406c3363.dtsi
 create mode 100644 arch/x86/dts/microcode/m01406c440a.dtsi

diff --git a/arch/x86/dts/microcode/m01406c2220.dtsi b/arch/x86/dts/microcode/m01406c2220.dtsi
new file mode 100644
index 0000000..cf17dea
--- /dev/null
+++ b/arch/x86/dts/microcode/m01406c2220.dtsi
@@ -0,0 +1,4308 @@
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x220>;
+intel,date-code = <0x1142015>;
+intel,processor-signature = <0x406c2>;
+intel,checksum = <0x21a02433>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x20020000	0x15201401	0xc2060400
+	0x3324a021	0x01000000	0x01000000	0xd00b0100
+	0x000c0100	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x20020000
+	0x00000000	0x00000000	0x14011520	0xe1420000
+	0x01000000	0xc2060400	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x17ce1b3d	0x74fb4eb5	0x2f27d633	0x14060671
+	0x6b4d57b0	0xaa1ad327	0x6022d785	0x5fa91aad
+	0xef44e4c3	0xf91d4958	0x230883b7	0x7382ab6e
+	0xf14324ef	0xf94c28d7	0x9131d196	0xebcf2faa
+	0xc049cb37	0xd1577abd	0x5edbe45a	0x17e1ca1e
+	0xbe9a92c3	0x1c8e1790	0xb3c08b8a	0xca799851
+	0x3f2a8c92	0x1b7e15d8	0x1f44ecb2	0xaeda1838
+	0x0ace8669	0xae9d497e	0x424c680c	0x21b3a3ed
+	0xd924acfe	0xddc126a2	0x26363596	0x21cd999b
+	0x193f9df3	0x037d1953	0xf97a3dc5	0x4c94ad7e
+	0x98b360f0	0xeb90461f	0x438e6d2e	0x30851a0e
+	0xfd623681	0x18782d3c	0x702938c5	0x462df0dd
+	0xf7d67cc1	0x161076a0	0xf06e5db3	0xd861a76b
+	0xa40b06bc	0xed37c69b	0x2b25f98b	0x2b67887d
+	0xbf0131b5	0x571b7c25	0x34eb3752	0x992e406e
+	0x031ba8e7	0xccfc5b1d	0x33f487e9	0xeccc3098
+	0xe452737b	0xb38cc286	0x817bc58f	0x852a7fde
+	0xcbcd1b19	0xab11894a	0xa1f278d7	0x360829c9
+	0x11000000	0x67a4c01f	0x3f863221	0xf4b82fe4
+	0xf464c489	0x36b8d097	0xfa9ab17e	0x9bccf4e6
+	0x9f836ffd	0x647c263c	0x03c7bede	0xf20172e9
+	0x8bd6e772	0x8621aca5	0xbdf4eade	0xac27528a
+	0xb562042b	0x23d0304c	0x964558ea	0xb5c03c97
+	0xe0bd0467	0xe8a6d50a	0xe5d4b902	0xb164253e
+	0x8306959c	0xd1cd57d5	0xf7d1d586	0x4eb5152b
+	0xf488caca	0xaa47f32f	0x366676b3	0x96b27e47
+	0xc8f4fdda	0x9f6854bb	0x89921eb5	0xbb7fe720
+	0x59709d36	0x01a5880c	0xee526518	0x586055d6
+	0xfac43c7a	0x7ce6da62	0x301be309	0xf48c261e
+	0xdd7d6b27	0x6783c81a	0xf9151492	0x92a57bd1
+	0x94607cfc	0xd70700ed	0x18136034	0x16d26594
+	0xeadd5210	0xf2fa345f	0xba7e9be4	0x548b8db1
+	0xd9d81a27	0xb361bae3	0xe2c5c033	0xd34d0488
+	0x07925cd2	0xaf57a669	0xf7f634b6	0x58408a6f
+	0x2c8b4c46	0xe71e9a53	0x65bc42be	0x77db4bf1
+	0x4c839bf5	0xd6dbc641	0x4fbf6fef	0x6b71eb34
+	0x808898b9	0x7ecea348	0x608a1d5e	0x81225ea2
+	0x487a3d44	0xc2443f3e	0xff580d9a	0xefd915b1
+	0xe867848b	0x73c48e53	0x84d211d4	0x77a45152
+	0x146f95fc	0x088157cb	0x9661fa65	0x6b998636
+	0xd8d8748d	0x16bb32b5	0x3eb3be6a	0x29a2aa6e
+	0xcbd08ca6	0x74317789	0xe9e8f1ea	0x7c555679
+	0xd7f19a7b	0xcead34da	0xe584403c	0xbfae80e2
+	0x4e9a7a52	0x0eefa659	0x00eb4354	0xe6f0cf6d
+	0x69374a24	0xdb59e992	0x2d4a51eb	0x4cdb46ca
+	0x03613349	0x24d146ab	0x1cca9b58	0x6db9989a
+	0x534dedef	0xab90d703	0x75a8331b	0xec865e24
+	0x8415faf2	0x851022e8	0x4ee795cd	0x7af2b1a8
+	0x65ec359a	0x0a16c7d8	0x76d51f56	0x7e1e10ec
+	0xbab138d8	0x0d69389e	0x0a50fc3a	0x7746732d
+	0x98f692d2	0xf97254ff	0xd31185d4	0x1a7104b4
+	0x1382fbff	0x4660f775	0x187ed97f	0x880cb07a
+	0x566157d2	0x1ec58c53	0xc1fff1e3	0x30cde9d6
+	0x933993eb	0x365c5318	0x30a5df05	0x91744f18
+	0xac99ae3a	0xacb5cc81	0x6af06584	0xcbfcb5dc
+	0x10e3cdd1	0x8d31a621	0x36851aa8	0x718c1d81
+	0x4a574346	0x70fb532a	0xc97b70e3	0x4e61d0d1
+	0x9e5e2563	0xd86da543	0xb6c07a52	0x417e59f2
+	0xee4c48d6	0xca38e12e	0x9188a73d	0x6624af3c
+	0x62a1d33f	0xcf8afe37	0xd0173727	0x378470e3
+	0x35067424	0x0775c48c	0x7cab8eb0	0xfeb84d6c
+	0x187fbb8c	0xe2cab639	0xedfc3f59	0xbace1601
+	0xbc2535e9	0x74b7d16e	0xbc351b20	0xf4a41f6f
+	0x996a0c11	0xec1e5d06	0x8dae9d53	0xe92082ce
+	0x8bfb678f	0xb4ae58e4	0xbecbf0de	0xfdbd1df9
+	0x0cf5ffe2	0x362f4eb5	0x90cc7b4e	0x813a329d
+	0xd6b5c9fc	0x19dea293	0x4bc51036	0x10570f4b
+	0xd904d7b6	0x348da9e4	0x2fd7a32d	0xfc79b430
+	0x0b9c30dd	0xe0289eb6	0xc6ef55ef	0xfae73fe2
+	0xbd4a65d1	0x463804e8	0xc1d6c9d9	0xa94cea7a
+	0xa23f954d	0x2d76b17e	0x5851be88	0xcf829e51
+	0xe6c5c2a6	0x94f9772b	0xe6c22b45	0x3a6cb78f
+	0xb7f13d24	0x4c45d9f3	0xa8c115ec	0x3156aea1
+	0x8076cddc	0x191032dc	0xc7e3c577	0x04ff6b8e
+	0x4b048a66	0x61645b1e	0x49c1f2da	0x428518b8
+	0x5270837d	0x25aee268	0xa0d1bbaa	0x7c2b6cdc
+	0x95251e7d	0x47eb8833	0x4b274412	0x9df92f4d
+	0xc9165ad1	0x928605dd	0xed0ca542	0x59899c98
+	0xbe0a0295	0xaa9cc0ae	0x1a03db3f	0x00adb561
+	0xecfda91f	0xc4ba7882	0x38ec4207	0x55bc0855
+	0xced7c3e9	0x3e783ec0	0xe5085047	0x120366cb
+	0x56161c5b	0x2cda197c	0x4b855ae0	0xdebd39ef
+	0xe077f8c5	0x831346fc	0x119cf5bc	0x1f856af0
+	0x71be6741	0x94946c60	0x320ff78f	0xb24955bf
+	0xcaeaa452	0xcf673cad	0x83dee256	0xc1ca89d6
+	0x9a99b0c8	0x0506634a	0x43825141	0x93b261da
+	0x110fc9e7	0x1fff550f	0xff64e483	0x8ab28045
+	0xdc8a20e1	0x64f0125b	0x02b35cc1	0xae9a45a0
+	0x1ba02775	0x4ca78c43	0x00492b04	0xca28b4c6
+	0x2986d389	0x277de0ac	0x115a59fc	0x03c55ef6
+	0xeb2d37d4	0x8f6091a6	0x5589954b	0xd6a76cfe
+	0x52f90c11	0xc880f0aa	0x674e9009	0xd1cf458a
+	0xcbf97f4e	0x8b1a7a5e	0x52aca0bb	0x7562f0bb
+	0x27351468	0xf1ec9a0e	0x8300fefd	0x34358af1
+	0x1c33380b	0x29c5eae7	0x8ad5fedc	0x1fd8288b
+	0xb87a0fa8	0x0ed4830d	0x034a4536	0x9479d467
+	0xe6d0aafe	0x941d6d97	0x4e3b0d6f	0x057a6b8d
+	0x62cc8d8f	0xdcc01061	0x13217f10	0x6e5ddaa3
+	0xd9ebc375	0x1d54b3f2	0xed12af1c	0x48ff2428
+	0xe65ca319	0x6c699865	0x2d101e05	0xd28a495a
+	0x8bd948d8	0xa0b503b1	0x447158c1	0x662e03d2
+	0x0150fb5f	0x55288aa2	0x3e74f75d	0x5c111c33
+	0x802fe4c9	0x4d90bb9b	0x8b0a9377	0x9c215cdd
+	0x75602db3	0xf990e4a2	0xb41c8f6a	0x8a044b56
+	0x56214d80	0x95a51d94	0x957256ad	0xbc4bcfa2
+	0x82325276	0xe03231d9	0xb30b1dba	0x62974827
+	0x75c311f5	0x73081c86	0x6caedca9	0xfd65a79c
+	0x8a0a51b1	0x69f69434	0x1ec5f9ac	0x4379a9b8
+	0x25ee82e2	0xb8de5ce8	0x4dddef11	0x1f287f04
+	0x3438be45	0xa9f615c0	0xc4b4885d	0x4463603c
+	0x17a51586	0xb941900e	0x55f6b1fc	0x827adf71
+	0x2be9133f	0x98fcacec	0x7db549ff	0xf2172b4d
+	0x389a1ee7	0x28b04504	0x091e5333	0x9b3d5323
+	0xab29ddb5	0xf67748c3	0x838b320d	0xc2cd0deb
+	0x40b166b2	0xafe61841	0xbb915676	0x060235f5
+	0x68cbea2d	0xa7e4415c	0x9b67dcf9	0xd40da108
+	0xa6f53ede	0x395f766c	0xfd2b8267	0x84cbdd78
+	0x5dea645a	0x188cc462	0x471782c5	0x716f5c34
+	0x12b64f0a	0xc4e5d287	0x008469cf	0x74023871
+	0x280e14e8	0xa4cd2075	0xd6741c46	0x39228423
+	0x1d33880d	0x0fe5a8b2	0x09a0d784	0x43f282e0
+	0xe1fb9193	0x0c1d6d00	0x4618bb7e	0xa2346753
+	0xac82efb0	0x50c97aed	0x5e08b6da	0x1540d8d4
+	0xaaefaa57	0x0ae69a20	0x304ca040	0xc8e6ba4d
+	0x43b79690	0x5955117f	0x31e602b0	0xc650acbb
+	0x74fd2f1c	0xaa0ae398	0x83f8a97b	0xe2b2c874
+	0xfcb179bd	0xe2c54c23	0x1fa7d92f	0xfbafaf63
+	0xcc581a06	0x6a75505b	0xb1a35d63	0x9830e0e5
+	0xfdb7327f	0xa806c4db	0x0f146d1a	0xe848b52e
+	0x468a29bc	0x29ea4c2c	0x35ab0da3	0x0e81c222
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+	0x2ded8d3e	0xb9f69ba8	0xd7b2509e	0xe320a03a
+	0xa8da1ae2	0x0ce8a42e	0xf35334c3	0x0b16d14a
+	0x0ec31ece	0x21d6fc90	0x357c6d53	0x0660c479
+	0xd71b35d9	0x70b3dfc6	0xa04757cf	0xe7c480cf
+	0xb5cefffb	0x815596aa	0xa4fe1233	0xd40b51f9
+	0xcd65c934	0x9e410744	0x50943901	0xb9f64d34
+	0x765892c4	0xc37dcf44	0x4ca52be5	0x4150fc1a
+	0x6be637e4	0x09593fa3	0xf3c41aff	0xa2c5ab39
+	0xb34d6c8b	0x4f5959cd	0x192f572d	0x465e28d7
+	0xec9db016	0x4daf6f1c	0x8249efd4	0x54527d96
+	0xf053854b	0xaea0ff5a	0x4811f2eb	0xb0cb3314
+	0x015d9850	0x33f43296	0x9faa4a12	0x3c385258
+	0xe11c11c3	0x1efd827d	0xe41ad89d	0x3bd99c18
+	0xefb133e0	0x97727400	0x85c3e601	0x4ff46200
+	0xa224b0da	0x640a9f69	0xefb53b38	0x78cc66ba
+	0x24cf59a2	0xec0bea08	0x7e926b0e	0x2d921e46
+	0xd8e2e2ca	0x4cd53cdf	0xb82d08ae	0xe78c1e4d
+	0xca6734a5	0xe2e63cab	0xc5ba68fd	0xfa6cb0e5
+	0xeec04de5	0x459c0ddf	0x4ec808d6	0xe039961b
+	0x03696e0b	0x92c8caf5	0xa7e86d70	0x1f742b06
+	0x1d5cbd78	0x92d5578e	0x2e51bdd0	0x23346eb0
+	0xf05d39a6	0xc8fa8535	0x0384770a	0xce33dbcf
+	0xb9044bd7	0x9afdb602	0x4f22c8bf	0x4fd59c18
+	0xb04d1c2b	0x38b74c43	0x77a23a0c	0x579b9580
+	0x4890fb00	0x58a2e345	0x22420ca1	0x82aef8f1
+	0x4218f112	0xa0156339	0x44b5af22	0x96dafcb7
+	0xfed244ce	0x0ec0d7a8	0xa52e86f9	0x694248ed
+	0xd25870fe	0x34f93daa	0xe178d84a	0x70897ace
+	0xdfec9960	0x061729b4	0x1941e2d4	0xe88eded6
+	0x5657b452	0x5c98b677	0xf4f17162	0x996c3f42
+	0x61e22ac5	0xbcc504c2	0x841ab74d	0x35630385
+	0x0e5c2389	0xa77897fc	0xadd38e6f	0x03671090
+	0x2a94d2cc	0xa866a8a8	0x381068a4	0x0d8f769c
+	0x031cd3f4	0x43efbb62	0x65d26933	0x07c4c862
+	0x08bfe63f	0x63cf80fb	0x2bc411ea	0x1e53cdbc
+	0xccd46f61	0x7ae6f760	0x0a3794f2	0x7b8366b2
+	0x8781320d	0x4d49b28a	0xfe700e14	0xac5c041a
+	0x8a428c72	0xbeba1ba8	0x104ca0c9	0x2ecdd70c
+	0x99f94dd2	0x8c9e8050	0x2cdc1187	0x8697667a
+	0x39963209	0xbd6a1e9d	0xeb57f0d9	0x9c876cd1
+	0xde6cc752	0xc5d81dd8	0xcb04f322	0x3675e023
+	0x69f0ccaf	0xdc1c7299	0x66f6cc58	0x4af279a3
+	0x2405daef	0x3cdc114a	0xf11c038b	0xed163d84
+	0x8f915a3b	0x7a03313f	0x9abedf01	0xb828e02f
+	0x05d2d07e	0x36799491	0x1fbb66ec	0x215f0d93
+	0xa195c1f4	0xfd3cf434	0x4dd36fbf	0xfcbaeef5
+	0x5fa49ada	0xcfef09b7	0x9ca1f00f	0x1094bca9
+	0x2890356c	0x5535696f	0x3f786826	0xdfd166a6
+	0x7cc2a7bb	0xeb9775f7	0xf1f1d015	0x6cb43330
+	0x44f5103e	0x19cc238a	0xd802a783	0xa86d23b2
+	0xfc6d5595	0x406b04f8	0x1f87e63d	0x7def0a8c
+	0x66df4024	0x91291bd7	0xe7c9f664	0x3053efa6
+	0x13ae9ef3	0x1ca9934c	0x635e98b0	0xd7c0e7e8
+	0x951c1f5a	0x6a1f8310	0xe2e136b4	0x4fda9bf9
+	0x3748e217	0x201a3128	0xa77450a7	0x68a164db
+	0xbecaaa8b	0x39acdb6c	0xd72a8e99	0x358091fb
+	0xcbd44198	0xf8abf8d2	0x460d979f	0x09779fed
+	0xb066acb4	0xdd3b0b54	0xba6b34d1	0x9cd07e73
+	0xded39eaf	0x4a86f91e	0xa1576746	0xef5535c6
+	0x0d68d90d	0x9063b417	0x63764a13	0xe46589e8
+	0x4c464469	0x01da5cd7	0xda3d955f	0xa9cb6bda
+	0x74c5905a	0x022a3068	0x99785d4d	0x4aa81734
+	0x65f0e347	0x38cae44a	0x41445dd6	0xa8d298e6
+	0xe135a8c6	0x9e36cc39	0x450fd746	0xb4c9282e
+	0x5f902e54	0x52047a0a	0x054dcd41	0xa7f54f76
+	0x7e064c5d	0x1840b8dc	0xa42b3fc2	0x89959221
+	0x3670527e	0x0033bf58	0x6d01b3e7	0x153a4523
+	0xfdbede48	0xeb37591e	0xe9dcd198	0xe19b32b3
+	0x0ce76cc6	0x07fd8a8b	0x7861aea7	0x0e6ef7cc
+	0x295dcc81	0xeed43565	0x85e6b1b4	0x1c36176e
+	0x4de5e5ea	0xad417cd3	0xa0b502d7	0x4f4f26ad
+	0x55f0a11a	0x70414fff	0x578f513f	0x1a0036d4
+	0x65cb54d0	0xdbe91469	0xb613a236	0x73c05182
+	0x8da00dae	0xbc1c8526	0xff0ad02c	0x9289e4ef
+	0x245d0636	0x162603db	0x0e5a40fa	0x0cfeefd3
+	0xc355fae2	0xf2866c99	0xc65dfc8f	0xb7ab492f
+	0xf811fcf6	0xceaef429	0x4ecdb0e5	0x54bf4e1c
+	0x02c83d94	0x174cf22e	0x3c304b8d	0x9ad51572
+	0x444ab420	0x7c41fcb7	0x70193210	0xdc59b8da
+	0x9042a368	0x2c73167e	0x47dfb476	0xc07c86a0
+	0x0341e3aa	0x8ee97f19	0x65a47f28	0xe9221e76
+	0xac7ce5b2	0x5dc2293a	0x575436c1	0xb897b186
+	0xb6722e1b	0x0cede865	0x641884f8	0x87784739
+	0xb2cdbe39	0xf53210b5	0x819b5b5e	0x7e993c71
+	0x088c20d9	0x1ff3c97a	0xe348600f	0xb9434df3
+	0x4e2404ee	0x72ab1fb6	0x80922cc4	0x1239aa8b
+	0x180c6d70	0x47f0e6c8	0x04c35fa4	0x861eee82
+	0x4a5b0130	0xd29740e4	0x1200e288	0xd8aa1b4a
+	0x45cf055b	0xf0970e66	0x7e82c921	0x038a1be7
+	0x0f12a078	0x89ad1d6a	0x1c97ef2b	0xd3a3abb8
+	0xd6026f4e	0x2b9e13d4	0x5d5611d7	0xb35b1222
+	0x6a0715d6	0xe93cceea	0xbdc957a3	0x998dad9d
+	0xecfec721	0x09f02421	0x4c971582	0xe4fc588d
+	0x3a8f1c64	0xaeb5a6de	0x94bdd5e3	0xca0c1072
+	0x352fd723	0x6257b138	0xfee44d09	0x9a3d6c87
+	0x1031ae4d	0x6f2ebcac	0x97611fc4	0x37799303
+	0x9566d4f0	0xf6a69a64	0xd089ecc2	0x06c7a3b0
+	>;
diff --git a/arch/x86/dts/microcode/m01406c3363.dtsi b/arch/x86/dts/microcode/m01406c3363.dtsi
new file mode 100644
index 0000000..a90f21c
--- /dev/null
+++ b/arch/x86/dts/microcode/m01406c3363.dtsi
@@ -0,0 +1,4308 @@
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x363>;
+intel,date-code = <0x12182015>;
+intel,processor-signature = <0x406c3>;
+intel,checksum = <0x3ecdece5>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x63030000	0x15201812	0xc3060400
+	0xe5eccd3e	0x01000000	0x01000000	0xd00b0100
+	0x000c0100	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x63030000
+	0x00000000	0x00000000	0x18121520	0xf1420000
+	0x01000000	0xc3060400	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x6abbab24	0x789752cb	0x83003819	0x616df082
+	0xf0952c2c	0x7fbf7fbe	0xe1ca9540	0x47bb7ec7
+	0xef44e4c3	0xf91d4958	0x230883b7	0x7382ab6e
+	0xf14324ef	0xf94c28d7	0x9131d196	0xebcf2faa
+	0xc049cb37	0xd1577abd	0x5edbe45a	0x17e1ca1e
+	0xbe9a92c3	0x1c8e1790	0xb3c08b8a	0xca799851
+	0x3f2a8c92	0x1b7e15d8	0x1f44ecb2	0xaeda1838
+	0x0ace8669	0xae9d497e	0x424c680c	0x21b3a3ed
+	0xd924acfe	0xddc126a2	0x26363596	0x21cd999b
+	0x193f9df3	0x037d1953	0xf97a3dc5	0x4c94ad7e
+	0x98b360f0	0xeb90461f	0x438e6d2e	0x30851a0e
+	0xfd623681	0x18782d3c	0x702938c5	0x462df0dd
+	0xf7d67cc1	0x161076a0	0xf06e5db3	0xd861a76b
+	0xa40b06bc	0xed37c69b	0x2b25f98b	0x2b67887d
+	0xbf0131b5	0x571b7c25	0x34eb3752	0x992e406e
+	0x031ba8e7	0xccfc5b1d	0x33f487e9	0xeccc3098
+	0xe452737b	0xb38cc286	0x817bc58f	0x852a7fde
+	0xcbcd1b19	0xab11894a	0xa1f278d7	0x360829c9
+	0x11000000	0x34af9103	0xd674d0ce	0xa551e6a8
+	0xa4ecdc9d	0x1cc02761	0x9c6e5450	0xa160c598
+	0x52f99daf	0xec0347b8	0x3da61ab4	0xf567197c
+	0xfd8bb83f	0xcc995bef	0x54d178b6	0x1671de11
+	0xac092895	0x9debbed1	0x6c92142c	0x6323623d
+	0x0eb91ca9	0x5c295220	0xfbaa9c0e	0x589cb9fc
+	0xec23fbf8	0xa4a586a7	0x199f007f	0xdf3216db
+	0xc0d57da5	0x5f4725e3	0x5726d9c9	0x17667c8d
+	0xc1c79708	0x9e2256eb	0xfdd0d08f	0x60c7bed3
+	0x5845511d	0xd7082ef8	0x3baa9a81	0x79e5bbdb
+	0x5fa1d140	0x1a9dd574	0x65ab8603	0x3d09b760
+	0x5d5370dd	0x20cbfc54	0x6bb53528	0xd0d59569
+	0x3072c8e0	0x8d041e8a	0x393ff37c	0xa924e167
+	0xdc321c2e	0x758ef7f9	0x75d45a77	0xa162493e
+	0x541efc10	0x10adfa66	0x1ec98113	0x2adbfc4e
+	0x6f72ee57	0xb6135602	0x6bb1aaa5	0x8b28671d
+	0x52cd7438	0xe23e5714	0x541d71b8	0x1edeaecd
+	0x66099798	0x273aafe2	0x94c4bcfa	0xd2a91918
+	0xbfb900b7	0x7bffd9a6	0x98f3cc81	0x25418789
+	0xe4827c24	0xf91a6587	0xa8f37dce	0xed2bb02a
+	0x55e3d863	0xf75d0279	0x2d08e3a9	0x04447fc8
+	0x5b8a7d2d	0x7feac814	0x49f424a3	0xf3875991
+	0x7ba76639	0x15c5c756	0x351ce3b5	0x3f6c510c
+	0x99f05511	0xbf82e8cc	0x3a08ff2e	0x27ce0320
+	0x156823c8	0xea93277e	0xd4f644ee	0xed19db7c
+	0x883aa3cc	0x477659d8	0x328f8021	0x5f5027be
+	0xdc5dc6b0	0x7be0a222	0x3eeac5c3	0xd550feb0
+	0xe536e7f1	0x286636de	0x853b327c	0x89c0fb10
+	0xf3ca1f99	0xdfac434b	0x77629984	0xbf9089ab
+	0x4c485305	0xeeb11fc0	0x287f76db	0x30930095
+	0x6903c661	0x2b8cdcc7	0xdde71952	0xe608b18c
+	0x92c949a1	0x8aad2b8f	0x65862768	0x9cee8ac0
+	0x823d78c3	0x847136fe	0xd9310ed3	0xb8b42493
+	0x29ace469	0x42888461	0xded8e619	0xdf05ba83
+	0xbdff529b	0x200b50aa	0xa68969a3	0x852839f8
+	0xe990c70b	0x4646940c	0x97d3cc15	0xfbc684fd
+	0x670dc5bb	0x9221de80	0x4c8e6b5f	0x0d8e97a0
+	0xad70fce0	0xeae31c56	0x285bf809	0xe8875db3
+	0x90b80642	0xd3823067	0xcc83a749	0xf9ca429a
+	0x67422236	0x1391a167	0x0bf82b36	0xc9765751
+	0xe716e34a	0xe0a8a4f3	0x98c3a88c	0xc6e2f8a4
+	0x7fac67f1	0x1dc95999	0x506bbfcd	0xca368479
+	0xb40279c4	0x55bcf309	0xa33edb78	0x82136a30
+	0x5b12a8f7	0x760c01d3	0x5db7a4db	0x74f5bbf7
+	0x88d8cf63	0xbc44938d	0x3b8aa64c	0xa619841b
+	0x938ef7b6	0x4e62db80	0xec29b936	0x12c88360
+	0xd13fd368	0x049fedc3	0x980d670c	0x751d7334
+	0xe275082c	0xa856923e	0xcf718388	0x91c05a55
+	0x1feea2d0	0x973e9ef4	0xfdb50bdb	0xc9f0d356
+	0x1fb535f4	0xac8935e1	0x54ca8daa	0x5236b3f6
+	0x96077418	0x7cd145ee	0x4c3eac4c	0x96708111
+	0x2d0d2818	0xdf8d4d8c	0x1e0dc74d	0x55563148
+	0x8ded787c	0x8b23817c	0x2791cb6b	0xfe592eeb
+	0xc291504a	0x594803f6	0x5cb40c93	0x0fb42830
+	0xdc805110	0xa04177c6	0x5b196cff	0xa8389595
+	0xc22006a4	0x48f63bed	0x956fe2ab	0x8326bac5
+	0xf607d430	0x4db75e7c	0x5abe98f3	0x1ce11559
+	0x9a6bf85a	0x38332b5f	0xd5d89037	0xc68921c6
+	0xa0076717	0x7a8825e0	0xeca2298b	0x78202f5f
+	0xe9fb2a84	0x0a190fbb	0xacd7c21a	0x7c1b5df8
+	0x8bec1b4c	0x269507e6	0x8890150a	0xaba688e7
+	0x3bfe89e6	0xa2b9f1c1	0xe073b921	0x8886f1ec
+	0x8e70e13e	0x32a1a95e	0xaf7eb731	0x76ef3515
+	0x4e90039d	0x8e469581	0x076c7437	0x136549ac
+	0x357e3610	0x63a28516	0x19d505b8	0x43c971a6
+	0x0472035b	0x756164f2	0xbe6062a4	0xa1c37b2d
+	0xb07d2cf8	0x8476f6b6	0xc715da8d	0xb2afed44
+	0x249f6d7c	0xb5d69bab	0xcebfac4a	0x79dbe92b
+	0x27885a7a	0x36e23920	0x22974454	0xdb75e82a
+	0x9ed157a9	0x66b7f446	0x8dd61b49	0x1ec542a6
+	0x2f1602c7	0xfef7c1f0	0xf0e03fd1	0x7c5d27ba
+	0x1aab9e49	0x320c70a0	0x8428e51f	0x6518c994
+	0x4b1dd367	0x43e7759e	0x2e3a273b	0x02e96af6
+	0x7d7fd596	0x76fb392f	0x01e0575a	0x34c3c159
+	0x58ad09c1	0xff429aa9	0x542c728e	0x960c1be4
+	0xd993a44d	0xbe66f3b0	0x097dffa0	0x63ffa221
+	0x4e9d0eeb	0x059ac1e7	0xc8a98f69	0xba154f66
+	0x4c32444b	0x16c6b875	0x90ece67b	0xac649e61
+	0x9e8f0cf7	0x428e6df3	0xc9ceb8ef	0xa66bab0f
+	0xd499148e	0xbc453d7b	0x10064f2b	0x839a2b6d
+	0x8cf150bf	0xef4ff034	0x5f760dad	0x3ca17566
+	0xc469b66b	0x59389505	0xe731e5ef	0x436cf37c
+	0x07430a9d	0x4ec457cc	0xbb9b3569	0x39e66440
+	0x51508550	0x14e9282f	0x9019d229	0x4f1f91a8
+	0x52ed0975	0xb0f8c69e	0xc95dd930	0x58613f85
+	0xef94c1bb	0x4763c396	0x0271e452	0x199cf8f5
+	0xb5459017	0xd30a46f7	0x4a882adb	0xd81c67fe
+	0x560d3066	0x1c54e221	0xcff36db6	0x10ba2ad6
+	0x2a2f3b5c	0xb49815be	0x23d8e3a1	0x199ace76
+	0x14cabe0d	0xdcdb74ec	0x7ba0ee4e	0xcd8ade16
+	0x6fff6e9b	0xe7ebf779	0x3cd0d4bd	0x1d5988ba
+	0x41a869e6	0x938f3f7c	0x1c32d1cb	0x32cd7d32
+	0xd5f6c5b5	0x18f6ce02	0x355e6a02	0x1ce3fe19
+	0xef2db61e	0x53569367	0x2143daf2	0x9ff48c31
+	0xa8f2ae31	0xb942b0c5	0x5322e9fd	0x5c86f025
+	0x4564eb04	0xbf84637f	0x72649b68	0xbcfa9479
+	0x92160cd7	0x6a82f2ed	0x56e95854	0x8de8854e
+	0x3a6f9ae7	0xc600810a	0x3b916a72	0xc7757b0b
+	0x5c509f76	0x671a3e65	0x557be597	0xbfa43c40
+	0x75ad1bd1	0xef6e4e5e	0xc925131b	0x0b23f0df
+	0x8872d439	0xe7c68436	0x66948273	0x52c5820e
+	0x8bcdd308	0x5961f832	0x8b9e05b3	0x1877dc15
+	0x677c923f	0x9275f82c	0xb63ab226	0x2ebed52f
+	0x709be956	0x029efa11	0x181b9d17	0x85b196bd
+	0xd0ef2b24	0xdb40ed0f	0x64cd9131	0x6d4591ce
+	0x39b07cad	0x5d93a4fa	0xc72ab75f	0x411c103c
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+	0x06b432d9	0x5fddc685	0xfd7acfac	0xace4443d
+	0x569a1a6a	0xbc445236	0xecc5cc92	0x151182ec
+	0xe574f5ec	0x2c56e2bc	0x2af5abce	0x4339c30c
+	0xb55188b9	0x23698d98	0x60820baa	0x93ff7340
+	0x94c3333a	0x20f0e87f	0xab1d9fba	0x35834bea
+	0xd154a699	0xe320890a	0x85bf556d	0x42a2849c
+	0x7ba110dd	0xaee94e55	0xc790062b	0x78a8c168
+	0x66b1329d	0x0b527436	0x012da168	0xd2f0ee39
+	0xb679c867	0xca0a6921	0x940ccadb	0x6946498a
+	0x768d5174	0x5e7fba38	0x383f7c89	0x5c567fb2
+	0x310f24d4	0x4db03e90	0xd1bf21ac	0x8f15e7d0
+	0xa4d86530	0x8044a876	0x91f5130d	0x398f16ff
+	0xc7c1e0e6	0x9938b166	0xe3268899	0xefc1713a
+	0xe57529c5	0xfc878166	0xecf72ded	0x95ddaadc
+	0x0b391002	0x48d721e1	0xc5d1c59c	0xe7b1bebb
+	0x32fc2599	0xef46e6af	0x988769f1	0x71acab79
+	0x490080ac	0x10056692	0x2e11eb27	0x5acacf81
+	0xeae43c4f	0xc9e639d4	0x42d4c5c4	0x950606cc
+	0x3724a3dd	0xaced0ab2	0xccf75ff8	0xa27ca076
+	0x3bd73ecb	0x843f6982	0x48bc7011	0x460fa891
+	0xff7040a1	0xefdec3b5	0x4e32c53c	0xee9410f1
+	0xff88acac	0x38ceac92	0xcd7eee13	0x0fb5c53a
+	0xe6051d62	0xae5cecac	0xe98ab365	0x3c6f4ab6
+	0x3805e767	0xe0afc6cc	0xbb50a97e	0xd77e3cde
+	0x11461b04	0xe3596b3e	0x2462e279	0xd3ce1706
+	0xf5d951bd	0xac5d54e4	0xc5b0e96a	0x4d278b29
+	0x32bf069d	0x5af0d8c8	0x774c9588	0x86541549
+	0xb784a57b	0x62041d1e	0x84fec5e2	0xe7a02d73
+	0x1d74f2a9	0x611e0553	0x3b1d3821	0x1145d1fa
+	0x6c9eb1cc	0xa206315e	0xd144fc48	0x73847ca1
+	0x5029d400	0x7cd55815	0x1b144927	0x9cf7c04c
+	0x9643ea87	0xb16eb72e	0x3aa8837b	0xe8da7e89
+	0xe7da78db	0x5e50528c	0x3da12100	0x1b485ad1
+	0x1b21c0b9	0xb7bd623a	0x01350aa0	0x9ef31e71
+	0x2fd41bdb	0x7c65f063	0xe643f189	0x855b2c38
+	0xfd39766e	0xa29166da	0x85cb19c3	0x0553eec2
+	0xc3981002	0x05c026b5	0x0e6d7f4e	0xe45eda9e
+	0x4a8d4a53	0xf7c0d328	0x7ec10195	0x48aabc2d
+	0xa5162132	0xd673f0d3	0x28370129	0x386ca94f
+	0xc5e4fcab	0x63c14f79	0x156e44ff	0x4ef699dd
+	0x636756ef	0x4e4d0bb3	0xd29b405c	0x91efa47b
+	0x97ed6b3d	0x00f84348	0x0fcc73d8	0xbf412254
+	0x9e13a7e8	0x4fe9d1e1	0xa5f6f2cc	0x41d448a0
+	0x7ec7bad5	0x47656169	0x306ef8e0	0xeda02d50
+	0xc2fe9304	0x7ea7402f	0xb2165f5a	0xe36f3293
+	0xd2bf7174	0x64c1d01c	0x35331b08	0x8815ce43
+	0x0a860ec0	0xf000b1e2	0x22bba533	0xd2466bfc
+	0xfb50c4ee	0x59c255a6	0x08ede5c6	0xae11af6b
+	0x21c567f8	0x2deda390	0xf582c770	0x32a71f68
+	0xe5ca38bd	0x9911a225	0xeff94cde	0x66620d38
+	0xab8bc0c1	0x1682c8bf	0xf4822ea9	0xbbcd0d23
+	0x33bfde90	0xaee20724	0xa257d4ab	0x11802b6c
+	0xb1b1b529	0x31c2d8e8	0x00aa517d	0x4289c462
+	0xfa2fa42c	0x72557fc0	0xb0a54dbb	0xd5fc3e96
+	0xc07e39c3	0x93c0971a	0xa3abd61d	0xb5ad71de
+	0xb195e2c0	0x90e6594d	0xf86668b4	0x1c2f6270
+	0xc77d4f3b	0x6a37da20	0x420517a3	0x1cb5a1f4
+	0xdd65a884	0xd25f8295	0x7e4b9e1a	0xf9218723
+	0x14c15112	0xf5494da7	0x115c0604	0x2ebe1653
+	0x38a7a4c9	0x65d309e1	0x699bd062	0x3ac861b8
+	0x27172a07	0x1bf1ef7d	0xe84020c7	0xf6789173
+	0x9b74b780	0x925900b9	0xd05be0a5	0xccf0d5f9
+	0x7aa80fbe	0x590af161	0x12d33a9a	0xc301a2bb
+	0x27852617	0x277ba895	0xaf4925e4	0xed32ceea
+	0xa577e5e1	0x7d8ee645	0xf7e7afab	0xf4399460
+	0x0f2918e0	0x6f3ebf38	0x6b850f99	0x220658ae
+	0xbbd7637d	0x650f7053	0x7cf7d110	0x9ccea7af
+	0x79a727d6	0x80e9ed94	0x1bf513d8	0x1ab6e5f6
+	0xb4d31711	0x7912ac20	0x9e27d831	0x322ffb9b
+	0xdd8ef385	0x9738f2c6	0x2fd86982	0xf4e8c2c9
+	0xde9db8b1	0x5539d392	0x677fc7a6	0x2c5eb135
+	0x6db4c192	0x9da897e6	0x627d966e	0xed9b7993
+	0x969ca010	0x784e3016	0xda8678d3	0xdc1f0963
+	0x4e7ff6f5	0xb14d0966	0x552e1b93	0x68a43b8c
+	0xa2236345	0xa9b56c06	0x2d07cd9c	0xb6956632
+	0xd779e7a7	0xeccd2305	0x6bf60f0c	0xea0b32ad
+	0x14ea130b	0xb30ee5a9	0x8e076029	0x473f2043
+	0x051b275e	0x415bf046	0x9428b049	0xfa732499
+	0xd8419bf6	0xd4841843	0x2bf32829	0x3fbe2cda
+	0x6faa0fcf	0xfb282345	0x6ed0c2f3	0x08b172fe
+	0xd78bb73e	0x850b4c41	0xd3e9b902	0xc606fc7e
+	0x069dcaf6	0xc8ddc1f5	0x07f3fe56	0x98f43217
+	0xd111880b	0x7280be17	0xc19c6d05	0x28546554
+	0xb38a24cb	0x933951fe	0xef7b0e5f	0x2c0c01cb
+	0x7a8436df	0xee6b863c	0x8f33f6d4	0x861541a1
+	0x53685709	0x86f04b0c	0x7d592b84	0x04846350
+	0xb67cede9	0xdc297b9b	0x08e1ed70	0xe9306e22
+	0x013e379b	0x6635c475	0x00b95612	0x37514ad9
+	0x8c86123e	0x69c21346	0xe7b3d1dc	0xc09150a5
+	0x94b115c8	0x5799e5eb	0xf69cc4f8	0x3646b963
+	0x05e73f71	0x056f7937	0x4858bd19	0xf0cdbcbf
+	0xb7aac562	0x716a0b2d	0x849328dc	0x79bf0fa8
+	0x5092c51c	0x4b43622d	0x10d60769	0x6f981f1c
+	0x163b2b7e	0x210b0d12	0xc905e28b	0x139c2e1b
+	0x39e7ac9a	0xfdea5974	0xd240ee81	0x00b605d6
+	0x5cf6da6d	0xf6e5864c	0x538e2b3a	0x0b68a4d9
+	0x1542f8aa	0x22fdc4b0	0xce0727d9	0xc00509c0
+	0xe2e9da83	0x85e58cd3	0xc3a4cc2a	0x05b733d9
+	0xd142b1b8	0x9b50b224	0x24a4f235	0x7e26e4ff
+	0x72d74616	0xa8118811	0x845249c8	0xb385bea6
+	0x9ae48f64	0x4f3fc38c	0xfb92d503	0xb348fd91
+	>;
diff --git a/arch/x86/dts/microcode/m01406c440a.dtsi b/arch/x86/dts/microcode/m01406c440a.dtsi
new file mode 100644
index 0000000..6fdf211
--- /dev/null
+++ b/arch/x86/dts/microcode/m01406c440a.dtsi
@@ -0,0 +1,4308 @@
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x40a>;
+intel,date-code = <0x12182015>;
+intel,processor-signature = <0x406c4>;
+intel,checksum = <0x5807e19a>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x0a040000	0x15201812	0xc4060400
+	0x9ae10758	0x01000000	0x01000000	0xd00b0100
+	0x000c0100	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x0a040000
+	0x00000000	0x00000000	0x18121520	0xe1420000
+	0x01000000	0xc4060400	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x624800aa	0xf01ac54c	0x5a84228f	0xcc79131d
+	0x9feff6a3	0x4a87b5a3	0xac874956	0x7dfe6197
+	0xef44e4c3	0xf91d4958	0x230883b7	0x7382ab6e
+	0xf14324ef	0xf94c28d7	0x9131d196	0xebcf2faa
+	0xc049cb37	0xd1577abd	0x5edbe45a	0x17e1ca1e
+	0xbe9a92c3	0x1c8e1790	0xb3c08b8a	0xca799851
+	0x3f2a8c92	0x1b7e15d8	0x1f44ecb2	0xaeda1838
+	0x0ace8669	0xae9d497e	0x424c680c	0x21b3a3ed
+	0xd924acfe	0xddc126a2	0x26363596	0x21cd999b
+	0x193f9df3	0x037d1953	0xf97a3dc5	0x4c94ad7e
+	0x98b360f0	0xeb90461f	0x438e6d2e	0x30851a0e
+	0xfd623681	0x18782d3c	0x702938c5	0x462df0dd
+	0xf7d67cc1	0x161076a0	0xf06e5db3	0xd861a76b
+	0xa40b06bc	0xed37c69b	0x2b25f98b	0x2b67887d
+	0xbf0131b5	0x571b7c25	0x34eb3752	0x992e406e
+	0x031ba8e7	0xccfc5b1d	0x33f487e9	0xeccc3098
+	0xe452737b	0xb38cc286	0x817bc58f	0x852a7fde
+	0xcbcd1b19	0xab11894a	0xa1f278d7	0x360829c9
+	0x11000000	0x242e4460	0x190ba541	0xd3a20d0c
+	0x7de0fc1d	0xafbe0a08	0x3233d6f4	0x82d82901
+	0x12c67fea	0x927c5686	0x8d45c03e	0xdb650016
+	0x88e39816	0xa493cdea	0x81a87c12	0xadbd5724
+	0xd402794b	0xdde114da	0xa32c6058	0xd820b63c
+	0x712726d9	0xf99787b2	0x1b8628b6	0xbd4c94ff
+	0x70952446	0xa00d56ba	0x36911787	0x5f3ca7d7
+	0x7cc87a67	0x10c77f6f	0x63bb3eaf	0x85f294d3
+	0x3283b281	0x71c85eb4	0x69a72f05	0x5e0f08e0
+	0xdedd727a	0x8f300d0e	0xe1998f90	0x340f0e3f
+	0x8ce037fa	0x801f7160	0x671b364c	0x09c2ba50
+	0x6d506296	0x4760ba91	0x046e581b	0xd5711e70
+	0x58c7279b	0x4376b9b5	0x63cabe1e	0x9c22ec14
+	0xb6752bf0	0x1b4da16f	0x09a0c65f	0xc6dbaf78
+	0x04e7d9aa	0x20895400	0x9516e20b	0x8cb87942
+	0x16f1e580	0x4dc7b3c0	0xec4ea2a3	0xd57a22c3
+	0x51306f3f	0xa9ef572d	0x261efc37	0x9d9e7b4a
+	0xe3024514	0x4a2e2c58	0x3a77c165	0xafab4790
+	0x6ce34d1b	0x04f0ab75	0x2d437f08	0x1d790312
+	0xbac94faa	0x976b9ce9	0xf770def7	0x6ed8427c
+	0xce8a6521	0x1ec7251b	0x10379d55	0x882b8ef8
+	0x58c4e197	0xb2c48b35	0xb3311655	0x8ccdf15a
+	0xf4368e46	0x5e41fe36	0xc6eae59d	0xe4b01c2d
+	0x506e5bc1	0x522095cb	0x32c19087	0x67d400ab
+	0xc46ca675	0xd1b4dc87	0xc41aaf74	0xb75e5de1
+	0x53588482	0x6e168b15	0x3cf9d2eb	0x2a26c991
+	0x868d92e6	0xefd21291	0x0d7d393b	0xd28a6693
+	0xbf850f8b	0x8bab78fa	0x06ef9ab5	0x96bf071e
+	0x4de55407	0x72997fcb	0xc6416709	0x9ba6d026
+	0xf8d588bc	0xbbacd314	0xdbb65892	0x49ce4e3f
+	0x9f7f23c6	0xf3bfb271	0xe3b039ef	0x9721d9d2
+	0xcfeff460	0xf9770555	0x8ecbd41f	0xdbc8de19
+	0x7f16eff1	0x50702a87	0x4e893e88	0xd0fe5546
+	0xd75c268d	0x3b325a3e	0xccb8f848	0xf116b116
+	0xd53bc36b	0x69c3fbca	0x78fca5a7	0xde29e62a
+	0x087fe22c	0xa2341056	0x4d8e470c	0x0897e8e0
+	0x1231c549	0x29fe1948	0x1510df78	0x27dfdf9f
+	0xfa7ac39d	0x02a2d8a3	0xf4e92fcc	0x65f8a856
+	0x0a620586	0x9d8168c6	0xfc2b73e8	0x51aa73cf
+	0x790d1ff2	0xe2eec1ee	0x2b6bf6ae	0x016d719f
+	0x4299ce1e	0xf5b6fb08	0x616eeef7	0x58e7838a
+	0x983a59c5	0xaab03473	0xb493c5cc	0x8f895d01
+	0x7eeb95ed	0xc751e74b	0xd56b648c	0x73397d44
+	0x2044779e	0x76ebf0ac	0xde6e453d	0x314e2211
+	0x75da63a0	0xaebc257e	0x3ed500ca	0xcb90731f
+	0x0e061298	0x202e853c	0x5475c57e	0xf7d590c9
+	0x50d855ad	0xa9a1740a	0xad86458c	0xac935753
+	0x443950f0	0x679449c7	0xfecdc458	0xda126f52
+	0xf95db8ad	0xce83faca	0xd50e170d	0x8985c89a
+	0x21300e90	0x45681348	0x77d41f24	0x7771eae6
+	0x7c649019	0x776f433f	0x1176f3a2	0xba7771a5
+	0xac9add02	0x80a77d73	0x9d532385	0x32a3bf43
+	0x3812be26	0x5f0b64e2	0x661150bf	0x1cda3da3
+	0x25901706	0x5566fc2a	0x4196324b	0xdaf55897
+	0xa182d0d1	0x27753c5c	0x7ed91479	0x670dd712
+	0x79f5e8c5	0xc2a882f7	0x99387af4	0xfbc30997
+	0xb2cbb413	0xe205d416	0x9c380f50	0x3ba30c90
+	0xf80b317f	0x06b74c14	0x5b8780de	0x98735ad4
+	0x335d6f43	0xb2de8a5b	0xeab51ec0	0x6b9bb87b
+	0x49f621d9	0x6dee0720	0xa5a5fbf8	0x576383ad
+	0x8d9fb03e	0xc7c6836f	0xc2b98f2a	0x157973e9
+	0xc3054865	0xb5d5a8f0	0xb2a939d4	0xda7d660c
+	0x5bea5713	0xcd9fb93c	0xd04225a5	0x469c6ef5
+	0x6e1b2189	0xec2038a5	0x48d864c9	0xf96ad8b8
+	0xc311c9f4	0xf293d447	0xda23084d	0xc0cec16b
+	0x4fa98f1d	0x1d65cb44	0x25241ce4	0xec6e71ba
+	0x5c060508	0x864e7590	0xa7bdf4df	0x05fb9183
+	0x70a2ed5e	0x8a7bdfd5	0xea411027	0x19a6c9ff
+	0xcbbc17ac	0x401aa669	0xe6bf3370	0x72f681cb
+	0xbe77a1a9	0xbc6ae060	0x8378299a	0x926ee257
+	0xff603c73	0xdeecde51	0x519d6956	0x5c4c6dd0
+	0xfd29f3e6	0x846667e5	0x2105ef33	0x158f5778
+	0xb894867e	0x162fe780	0x70d1570d	0x27ce89cb
+	0x3bad8e45	0x439d8dce	0xe8667d8b	0x4d47880a
+	0x652c7019	0x5f414acc	0x4339c1a7	0x833ca27c
+	0x32c92aa1	0x243b00bf	0x8e50fe5f	0x7efc7591
+	0x2e0d41f6	0xc67c978f	0x87f2eb1b	0xdcf5e604
+	0x801c6f5c	0x3caaf323	0x82d252d6	0x99fe2e39
+	0xb76a1e41	0x134d9628	0xfc095714	0x45a0825f
+	0x48c60f59	0x2c959a36	0x3d60f4d7	0xe24a8f04
+	0xa3b5f596	0xd9e67450	0x186af1d5	0xa1a1bb77
+	0x031cbf72	0x273f96e1	0x6938dbd2	0xc9613d71
+	0x786056b4	0x41bfff37	0x90dc1359	0x88291b7e
+	0xe087ea2f	0x2a307121	0x8f9ce425	0xeaf83930
+	0x63b737a2	0x63e23ab1	0xbfd9e458	0x423603de
+	0x3fc30a6f	0xcb6142e6	0xa64299b4	0x61c68b5f
+	0x1ba06ed2	0x91887c3e	0xb9aff67f	0x64784f73
+	0x34b0824c	0xc12f97e1	0x94441a34	0xd2080b65
+	0xe1c21c9a	0xa74732a0	0xefa59483	0x5d8a01a7
+	0x1dd6c22e	0x4d480d8f	0xb63a8354	0xa72c3581
+	0xf1df301e	0x5b3f517e	0x26b2082b	0x2b41052b
+	0x9154629f	0xabc7702c	0x1025b356	0x9e85e8ba
+	0x1f544d99	0x2c8ec998	0xe4440160	0xb0deb1a3
+	0x201e3fe8	0x70a7792c	0xfcf41de1	0xe2b2e6aa
+	0x10fc055b	0x373e9fbf	0xffee3e7d	0x2d1baa79
+	0xdb411a57	0xf30ea568	0xe30497de	0xb4682d8c
+	0xb458fbd2	0x5d1d68de	0x02da095c	0x71471bce
+	0x543edc68	0x52187bde	0x98743b08	0x0674aa49
+	0x5dad1705	0x74b009a2	0x765840c7	0x3e1cf377
+	0x3ecbb54e	0x6d5934b9	0x8a67c9ac	0xe1a15fbe
+	0x6e096703	0x24fbe4b3	0x99c9e345	0xd2d520f3
+	0xc5aefea5	0xe9e828b9	0x4e8f47b2	0x92653def
+	0xa7b8249d	0x5f53eb02	0xe3233073	0x1c933c46
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+	0x35e67029	0x4030ed4c	0xe0cd63a3	0xda35976a
+	0x94fbc08c	0xd6d3429b	0x6ac3087d	0x57e3eb54
+	0xeba813a4	0x9bd06f05	0x2d2f860f	0x4901e70c
+	0x226802f5	0xcc8d0940	0xa8825eb5	0x1ab23757
+	0xe842caff	0x77123976	0x647068e2	0xc75de8be
+	0x0bf388a2	0x4f501ebe	0xc64118fc	0xc1cbaabb
+	0x98c9810d	0x0b4f63e4	0x641e2360	0x168bb3c8
+	0xa1cede7b	0x5fe0d436	0xa93a4cf8	0xf7b75424
+	0xf4725a08	0xe0532c1e	0xfe83bc98	0x3a43d6e0
+	0xbebecec8	0x81bd1a51	0x5525ecd7	0x384d8d37
+	0xed6ef639	0x5efe6032	0x6937ce1f	0xb3ee8dbd
+	0xa0aa97df	0xd62d6fd7	0x5acc6d6f	0xef19f5b1
+	0x3ad0d109	0x3660bbd1	0xfbf8d7e7	0x210ab474
+	0xd9cde94d	0x4cb35844	0xb287c427	0x6087b156
+	0xc04b25c1	0x78722325	0xe5937d3b	0x2477d2bf
+	0x859237aa	0xd29b1567	0xc4b6c1ec	0xb325f9d3
+	0xb59d3b11	0x54449fb8	0xba28f795	0xc72e0157
+	0xa306042a	0x974e4bf8	0x835a665c	0x4b54f87b
+	0x25b9f700	0x2176126c	0x868ad962	0xf5478e50
+	0xa82f2f84	0x1ef6e4af	0xbfaf0c9b	0xea6acebe
+	0x55965550	0x0d1a325d	0x9b786f43	0xa3a55c13
+	0x758e4290	0x0e156cd6	0xec3fa531	0x73464f29
+	0x1639e8bf	0x051d786b	0x303c214a	0x80c09001
+	0x71f5ec60	0xb5322364	0x91ea1fc2	0xb461fe47
+	0x596fbd60	0x73671c45	0x7301b951	0xb9c9605c
+	0x1b04f497	0xfbef823b	0xc621a97b	0xe55e1d29
+	0x6984e8b5	0xefce9254	0x544f7540	0xdcd81ef6
+	0xa20e4ad6	0xc80fb804	0xb96d8a3b	0x3d04128e
+	0xdcbd0f39	0xb5d4bca3	0x7720d158	0x6da9a045
+	0x273c430e	0xece0eb38	0x672e817a	0xc0d79da7
+	0x75c37954	0x58c753de	0xcbcbad35	0x786e6c7e
+	0xe260b5d1	0xc404468d	0x57cfae75	0x39b497a8
+	0x1bae57a2	0x52c7508e	0x89b127b9	0x03736bf1
+	0xd0af6722	0x10b7cad0	0xb2fec538	0xae1bee3b
+	0xb4fcc9f5	0xc7a89d3b	0xdde3aa84	0xef24259d
+	0x5adacacb	0xd7f953d6	0x0be41a0c	0x83d6fbb0
+	0x6967528e	0xb46394d6	0xf63ebf82	0xd2b3f03e
+	0x7b86862f	0x57786dba	0xeb06cbba	0x7e989a81
+	0xb9ebccbc	0xb74fffd4	0xbec943d2	0xb9a375c3
+	0xd3344f7a	0x26c60798	0x49016082	0x551f17e0
+	0x0f4bee9d	0x614303cd	0xcad6bd8c	0x5c3bbeaf
+	0x86f4d83d	0xfc4445db	0x0f1a79e5	0xb9f0ce8c
+	0xdc4152af	0x6e8fc82f	0xf2ccad51	0x8b0b7cc3
+	0xa2aa307b	0xa520ea29	0x0292bc09	0x534ffc75
+	0x1b398c80	0x5eca089e	0xc7aff269	0x0059f0b9
+	0x541aa484	0x99943f2a	0xfc1f579e	0x85da714d
+	0xd7092c5f	0x0a167a5d	0x898726b8	0x47ffe115
+	0x8990821e	0xc08ff8a0	0x0e1a2986	0x339ff1d0
+	0xedd4aaeb	0x9350e602	0x6569e126	0x5859aafd
+	0x5b0cb2c6	0x147cfa35	0x0d905917	0xf2233208
+	0xb36ef680	0x841b48d9	0x1c6a0f0d	0x8227247e
+	0xac9bbb04	0xff8bbb90	0x6fcea1ea	0x7dfbb3aa
+	0xa464bac7	0x88633a36	0x674b0362	0x74223977
+	0x139a8d87	0x1d8a5826	0xaa254054	0xeff8db68
+	0x664d29b7	0x5f1ac3eb	0xddcba2bf	0x0e73df53
+	0x08ffe947	0xbf3f1da8	0x46f1d718	0x5ab11692
+	0xf190a0b8	0x9d0e9717	0x86757018	0x97827999
+	0x573d0b1d	0x7bf3969b	0x3172eab5	0xc5dd90bd
+	0x413d1445	0xc9612206	0x43ecc87c	0x4d0af8fb
+	0xad744b83	0x8f007f86	0x44551cd7	0xaf820402
+	0x6b9a3cd7	0xed4a0a59	0xd4eb0493	0x1bde6215
+	0xa693b3fc	0x22e4fe0d	0x057a211e	0x9973169c
+	0x086516f4	0xe1e6ba26	0xb4ad5a0e	0xbf3cf264
+	0xa40e61f0	0x12eef468	0x7be11464	0x6acb81cf
+	0xa04787f7	0xdbe5ac75	0xcad096a8	0x185cf673
+	0x6e0ea343	0xe84a1467	0xef3f00eb	0xef177b01
+	0x46dd87bc	0x34309420	0x0821d1d1	0x39000215
+	0x685f4c0e	0xb80c1c87	0x9756d5ff	0xbbcaf5b0
+	0xde2d1453	0x4c9f69d1	0x56196e6b	0xef81e9a5
+	0xfc22f7ce	0xca61a7a6	0x4bf15020	0xfa080406
+	0xd0b837a6	0x7bcb8577	0xfedf367c	0xfcf81696
+	0x014ed3e6	0xf3353212	0xc062d44a	0xd813a68f
+	0xd5d7a1db	0x8c45c94e	0xc5b90467	0x6f74385b
+	0x7130a2d3	0x708b9489	0xdbbb7ce7	0xfc90865c
+	0x653c5bd4	0xac3cd1e2	0xe27bb6d9	0xd41e4d6a
+	0xae016134	0x87b7b2c9	0xd994b3e9	0x71e42004
+	0xb845d3af	0x592dbebb	0x620899c0	0x8d3b090d
+	0x9d0e6a42	0xce95d950	0x4b7117d0	0x4e32208e
+	0x379df4c7	0x73c8403d	0x9c035976	0x9fa4ab3f
+	0x0e4abd10	0xea5abdc0	0xc74b08f5	0x8ad84f2f
+	0xe6ea941f	0xedd37fd7	0x8800959d	0x4eaf1dd9
+	0xc03f8601	0x3f05cec7	0xa7dc9585	0xfc497aa7
+	0x5ab6ec8d	0xf920b15a	0x0528a3a0	0xb03478f9
+	0xf58d945c	0xf6d56911	0x9d6b8f61	0x62eced7e
+	0x8c387967	0xb9c3664c	0x703321a1	0xb0779fb6
+	0x0a5ca536	0x216262ca	0x8471e2dc	0x456035c2
+	0x1f9a3f80	0x62f7b45b	0xe0fb6e10	0xd817b0a1
+	0xb04007a7	0x8a2a3997	0xc13b2ff7	0xac042c3c
+	0x0af1158f	0xb080446d	0x22561f86	0x3c449de0
+	0xbe156e20	0x7745c38a	0x19cadbff	0xcf505afc
+	0xc2f94af9	0x720e8b00	0x1d740186	0xc411e6a7
+	0x16f99b0a	0x0b949e35	0xbc306cf9	0x67f417b4
+	0xce3e2635	0xd8f3a3fa	0x4b6fd9e6	0x63cfad21
+	0xaaf1456d	0x6c520541	0xca2dcac8	0xab62863d
+	0x150a0ae3	0xa9e92a07	0x85e51d1f	0x327253e7
+	0xa0d5d35e	0x331b43ce	0x207a336a	0x3407a0b3
+	0x975a2429	0x95d42c04	0x9ff5ef17	0xfefb14c7
+	0xa3d8f8ac	0x6a112cd8	0x2d276889	0x5f2f6ef9
+	0x611636e3	0xecc81a74	0x4d482888	0xa46a478d
+	0x7de65d9d	0x921e2a1f	0x48cca90f	0x64013e1f
+	0x45aa6b87	0x5da46878	0x39a21b74	0xa72250de
+	0xebbaa970	0xef8d31f9	0x59a9e1e2	0xd3403b97
+	0x1780ddca	0x731fa40f	0x6c2ba0fe	0x4f053afb
+	0x2cf0e873	0xb6a733a8	0xc2a2e53e	0xd2241962
+	0xcb981a05	0x4af04278	0x053d4e34	0x63d071b8
+	0x731b063a	0xeed8b331	0x05221e90	0x6705a444
+	0x2c504d6d	0x231c42ec	0x8debbfaa	0x07829ed7
+	0x50ee8337	0x17ed0270	0x4a04c200	0xf5e650bd
+	0x5bbe5f66	0x72d412d3	0x40253020	0xa949f29d
+	>;
-- 
2.9.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 11/13] x86: braswell: Add FSP configuration
  2017-08-16  5:41 [U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support Bin Meng
                   ` (9 preceding siblings ...)
  2017-08-16  5:41 ` [U-Boot] [PATCH 10/13] x86: braswell: Add microcode for B0/C0/D0 stepping SoC Bin Meng
@ 2017-08-16  5:42 ` Bin Meng
  2017-08-26 13:39   ` Simon Glass
  2017-08-16  5:42 ` [U-Boot] [PATCH 12/13] x86: braswell: Disable PUNIT power configuration for B0 stepping Bin Meng
  2017-08-16  5:42 ` [U-Boot] [PATCH 13/13] x86: Support Intel Cherry Hill board Bin Meng
  12 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-16  5:42 UTC (permalink / raw
  To: u-boot

Add FSP related configuration for Braswell.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/braswell/Makefile                     |   2 +-
 arch/x86/cpu/braswell/fsp_configs.c                | 158 ++++++++++++++
 .../include/asm/arch-braswell/fsp/fsp_configs.h    |  89 ++++++++
 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h   | 172 +++++++++++++++
 arch/x86/include/asm/arch-braswell/gpio.h          | 234 +++++++++++++++++++++
 5 files changed, 654 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/cpu/braswell/fsp_configs.c
 create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
 create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
 create mode 100644 arch/x86/include/asm/arch-braswell/gpio.h

diff --git a/arch/x86/cpu/braswell/Makefile b/arch/x86/cpu/braswell/Makefile
index 19bcee6..ddf6d28 100644
--- a/arch/x86/cpu/braswell/Makefile
+++ b/arch/x86/cpu/braswell/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += braswell.o cpu.o early_uart.o
+obj-y += braswell.o cpu.o early_uart.o fsp_configs.o
diff --git a/arch/x86/cpu/braswell/fsp_configs.c b/arch/x86/cpu/braswell/fsp_configs.c
new file mode 100644
index 0000000..d984519
--- /dev/null
+++ b/arch/x86/cpu/braswell/fsp_configs.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * Override the FSP's Azalia configuration data
+ *
+ * @azalia:	pointer to be updated to point to a ROM address where Azalia
+ *		configuration data is stored
+ */
+__weak void update_fsp_azalia_configs(struct azalia_config **azalia)
+{
+	*azalia = NULL;
+}
+
+/**
+ * Override the FSP's GPIO configuration data
+ *
+ * @family:	pointer to be updated to point to a ROM address where GPIO
+ *		family configuration data is stored
+ * @pad:	pointer to be updated to point to a ROM address where GPIO
+ *		pad configuration data is stored
+ */
+__weak void update_fsp_gpio_configs(struct gpio_family **family,
+				    struct gpio_pad **pad)
+{
+	*family = NULL;
+	*pad = NULL;
+}
+
+/**
+ * Override the FSP's configuration data.
+ * If the device tree does not specify an integer setting, use the default
+ * provided in Intel's Braswell release FSP/BraswellFsp.bsf file.
+ */
+void update_fsp_configs(struct fsp_config_data *config,
+			struct fspinit_rtbuf *rt_buf)
+{
+	struct upd_region *fsp_upd = &config->fsp_upd;
+	struct memory_upd *memory_upd = &fsp_upd->memory_upd;
+	struct silicon_upd *silicon_upd = &fsp_upd->silicon_upd;
+	const void *blob = gd->fdt_blob;
+	int node;
+
+	/* Initialize runtime buffer for fsp_init() */
+	rt_buf->common.stack_top = config->common.stack_top - 32;
+	rt_buf->common.boot_mode = config->common.boot_mode;
+	rt_buf->common.upd_data = &config->fsp_upd;
+
+	node = fdt_node_offset_by_compatible(blob, 0, "intel,braswell-fsp");
+	if (node < 0) {
+		debug("%s: Cannot find FSP node\n", __func__);
+		return;
+	}
+
+	node = fdt_node_offset_by_compatible(blob, node,
+					     "intel,braswell-fsp-memory");
+	if (node < 0) {
+		debug("%s: Cannot find FSP memory node\n", __func__);
+		return;
+	}
+
+	/* Override memory UPD contents */
+	memory_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node,
+		"fsp,mrc-init-tseg-size", MRC_INIT_TSEG_SIZE_4MB);
+	memory_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node,
+		"fsp,mrc-init-mmio-size", MRC_INIT_MMIO_SIZE_2048MB);
+	memory_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
+		"fsp,mrc-init-spd-addr1", 0xa0);
+	memory_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node,
+		"fsp,mrc-init-spd-addr2", 0xa2);
+	memory_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node,
+		"fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_32MB);
+	memory_upd->aperture_size = fdtdec_get_int(blob, node,
+		"fsp,aperture-size", APERTURE_SIZE_256MB);
+	memory_upd->gtt_size = fdtdec_get_int(blob, node,
+		"fsp,gtt-size", GTT_SIZE_1MB);
+	memory_upd->legacy_seg_decode = fdtdec_get_bool(blob, node,
+		"fsp,legacy-seg-decode");
+	memory_upd->enable_dvfs = fdtdec_get_bool(blob, node,
+		"fsp,enable-dvfs");
+	memory_upd->memory_type = fdtdec_get_int(blob, node,
+		"fsp,memory-type", DRAM_TYPE_DDR3);
+	memory_upd->enable_ca_mirror = fdtdec_get_bool(blob, node,
+		"fsp,enable-ca-mirror");
+
+	node = fdt_node_offset_by_compatible(blob, node,
+					     "intel,braswell-fsp-silicon");
+	if (node < 0) {
+		debug("%s: Cannot find FSP silicon node\n", __func__);
+		return;
+	}
+
+	/* Override silicon UPD contents */
+	silicon_upd->sdcard_mode = fdtdec_get_int(blob, node,
+		"fsp,sdcard-mode", SDCARD_MODE_PCI);
+	silicon_upd->enable_hsuart0 = fdtdec_get_bool(blob, node,
+		"fsp,enable-hsuart0");
+	silicon_upd->enable_hsuart1 = fdtdec_get_bool(blob, node,
+		"fsp,enable-hsuart1");
+	silicon_upd->enable_azalia = fdtdec_get_bool(blob, node,
+		"fsp,enable-azalia");
+	if (silicon_upd->enable_azalia)
+		update_fsp_azalia_configs(&silicon_upd->azalia_cfg_ptr);
+	silicon_upd->enable_sata = fdtdec_get_bool(blob, node,
+		"fsp,enable-sata");
+	silicon_upd->enable_xhci = fdtdec_get_bool(blob, node,
+		"fsp,enable-xhci");
+	silicon_upd->lpe_mode = fdtdec_get_int(blob, node,
+		"fsp,lpe-mode", LPE_MODE_PCI);
+	silicon_upd->enable_dma0 = fdtdec_get_bool(blob, node,
+		"fsp,enable-dma0");
+	silicon_upd->enable_dma1 = fdtdec_get_bool(blob, node,
+		"fsp,enable-dma1");
+	silicon_upd->enable_i2c0 = fdtdec_get_bool(blob, node,
+		"fsp,enable-i2c0");
+	silicon_upd->enable_i2c1 = fdtdec_get_bool(blob, node,
+		"fsp,enable-i2c1");
+	silicon_upd->enable_i2c2 = fdtdec_get_bool(blob, node,
+		"fsp,enable-i2c2");
+	silicon_upd->enable_i2c3 = fdtdec_get_bool(blob, node,
+		"fsp,enable-i2c3");
+	silicon_upd->enable_i2c4 = fdtdec_get_bool(blob, node,
+		"fsp,enable-i2c4");
+	silicon_upd->enable_i2c5 = fdtdec_get_bool(blob, node,
+		"fsp,enable-i2c5");
+	silicon_upd->enable_i2c6 = fdtdec_get_bool(blob, node,
+		"fsp,enable-i2c6");
+#ifdef CONFIG_HAVE_VBT
+	silicon_upd->graphics_config_ptr = CONFIG_VBT_ADDR;
+#endif
+	update_fsp_gpio_configs(&silicon_upd->gpio_familiy_ptr,
+				&silicon_upd->gpio_pad_ptr);
+	silicon_upd->emmc_mode = fdtdec_get_int(blob, node,
+		"fsp,emmc-mode", EMMC_MODE_PCI);
+	silicon_upd->sata_speed = fdtdec_get_int(blob, node,
+		"fsp,sata-speed", SATA_SPEED_GEN3);
+	silicon_upd->pmic_i2c_bus = fdtdec_get_int(blob, node,
+		"fsp,pmic-i2c-bus", 0);
+	silicon_upd->enable_isp = fdtdec_get_bool(blob, node,
+		"fsp,enable-isp");
+	silicon_upd->isp_pci_dev_config = fdtdec_get_int(blob, node,
+		"fsp,isp-pci-dev-config", ISP_PCI_DEV_CONFIG_2);
+	silicon_upd->turbo_mode = fdtdec_get_bool(blob, node,
+		"fsp,turbo-mode");
+	silicon_upd->pnp_settings = fdtdec_get_int(blob, node,
+		"fsp,pnp-settings", PNP_SETTING_POWER_AND_PERF);
+	silicon_upd->sd_detect_chk = fdtdec_get_bool(blob, node,
+		"fsp,sd-detect-chk");
+}
diff --git a/arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h b/arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
new file mode 100644
index 0000000..4b8521d
--- /dev/null
+++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+#ifndef __ASSEMBLY__
+struct fsp_config_data {
+	struct fsp_cfg_common	common;
+	struct upd_region	fsp_upd;
+};
+
+struct fspinit_rtbuf {
+	struct common_buf	common;	/* FSP common runtime data structure */
+};
+#endif
+
+/* FSP user configuration settings */
+
+#define MRC_INIT_TSEG_SIZE_1MB		1
+#define MRC_INIT_TSEG_SIZE_2MB		2
+#define MRC_INIT_TSEG_SIZE_4MB		4
+#define MRC_INIT_TSEG_SIZE_8MB		8
+
+#define MRC_INIT_MMIO_SIZE_1024MB	0x400
+#define MRC_INIT_MMIO_SIZE_1536MB	0x600
+#define MRC_INIT_MMIO_SIZE_2048MB	0x800
+
+#define IGD_DVMT50_PRE_ALLOC_32MB	0x01
+#define IGD_DVMT50_PRE_ALLOC_64MB	0x02
+#define IGD_DVMT50_PRE_ALLOC_96MB	0x03
+#define IGD_DVMT50_PRE_ALLOC_128MB	0x04
+#define IGD_DVMT50_PRE_ALLOC_160MB	0x05
+#define IGD_DVMT50_PRE_ALLOC_192MB	0x06
+#define IGD_DVMT50_PRE_ALLOC_224MB	0x07
+#define IGD_DVMT50_PRE_ALLOC_256MB	0x08
+#define IGD_DVMT50_PRE_ALLOC_288MB	0x09
+#define IGD_DVMT50_PRE_ALLOC_320MB	0x0a
+#define IGD_DVMT50_PRE_ALLOC_352MB	0x0b
+#define IGD_DVMT50_PRE_ALLOC_384MB	0x0c
+#define IGD_DVMT50_PRE_ALLOC_416MB	0x0d
+#define IGD_DVMT50_PRE_ALLOC_448MB	0x0e
+#define IGD_DVMT50_PRE_ALLOC_480MB	0x0f
+#define IGD_DVMT50_PRE_ALLOC_512MB	0x10
+
+#define APERTURE_SIZE_128MB		1
+#define APERTURE_SIZE_256MB		2
+#define APERTURE_SIZE_512MB		3
+
+#define GTT_SIZE_1MB			1
+#define GTT_SIZE_2MB			2
+
+#define DRAM_TYPE_DDR3			0
+#define DRAM_TYPE_LPDDR3		1
+
+#define SDCARD_MODE_DISABLED		0
+#define SDCARD_MODE_PCI			1
+#define SDCARD_MODE_ACPI		2
+
+#define LPE_MODE_DISABLED		0
+#define LPE_MODE_PCI			1
+#define LPE_MODE_ACPI			2
+
+#define CHV_SVID_CONFIG_0		0
+#define CHV_SVID_CONFIG_1		1
+#define CHV_SVID_CONFIG_2		2
+#define CHV_SVID_CONFIG_3		3
+
+#define EMMC_MODE_DISABLED		0
+#define EMMC_MODE_PCI			1
+#define EMMC_MODE_ACPI			2
+
+#define SATA_SPEED_GEN1			1
+#define SATA_SPEED_GEN2			2
+#define SATA_SPEED_GEN3			3
+
+#define ISP_PCI_DEV_CONFIG_1		1
+#define ISP_PCI_DEV_CONFIG_2		2
+#define ISP_PCI_DEV_CONFIG_3		3
+
+#define PNP_SETTING_DISABLED		0
+#define PNP_SETTING_POWER		1
+#define PNP_SETTING_PERF		2
+#define PNP_SETTING_POWER_AND_PERF	3
+
+#endif /* __FSP_CONFIGS_H__ */
diff --git a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
new file mode 100644
index 0000000..ecb01fa
--- /dev/null
+++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2015, Intel Corporation
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+#ifndef __FSP_VPD_H__
+#define __FSP_VPD_H__
+
+struct __packed memory_upd {
+	u64 signature;				/* Offset 0x0020 */
+	u8 revision;				/* Offset 0x0028 */
+	u8 unused2[7];				/* Offset 0x0029 */
+	u16 mrc_init_tseg_size;			/* Offset 0x0030 */
+	u16 mrc_init_mmio_size;			/* Offset 0x0032 */
+	u8 mrc_init_spd_addr1;			/* Offset 0x0034 */
+	u8 mrc_init_spd_addr2;			/* Offset 0x0035 */
+	u8 mem_ch0_config;			/* Offset 0x0036 */
+	u8 mem_ch1_config;			/* Offset 0x0037 */
+	u32 memory_spd_ptr;			/* Offset 0x0038 */
+	u8 igd_dvmt50_pre_alloc;		/* Offset 0x003c */
+	u8 aperture_size;			/* Offset 0x003d */
+	u8 gtt_size;				/* Offset 0x003e */
+	u8 legacy_seg_decode;			/* Offset 0x003f */
+	u8 enable_dvfs;				/* Offset 0x0040 */
+	u8 memory_type;				/* Offset 0x0041 */
+	u8 enable_ca_mirror;			/* Offset 0x0042 */
+	u8 reserved[189];			/* Offset 0x0043 */
+};
+
+struct __packed azalia_verb_table_header {
+	u32 vendor_device_id;
+	u16 sub_system_id;
+	u8 revision_id;
+	u8 front_panel_support;
+	u16 number_of_rear_jacks;
+	u16 number_of_front_jacks;
+};
+
+struct __packed azalia_verb_table {
+	struct azalia_verb_table_header header;
+	u32 *data;
+};
+
+struct __packed azalia_config {
+	u8 pme_enable:1;
+	u8 docking_supported:1;
+	u8 docking_attached:1;
+	u8 hdmi_codec_enable:1;
+	u8 azalia_v_ci_enable:1;
+	u8 reserved:3;
+	u8 verb_table_num;
+	struct azalia_verb_table *verb_table;
+	u16 reset_wait_timer_ms;
+};
+
+struct gpio_family {
+	u32 confg;
+	u32 confg_changes;
+	u32 misc;
+	u32 mmio_addr;
+	wchar_t *name;
+};
+
+struct gpio_pad {
+	u32 confg0;
+	u32 confg0_changes;
+	u32 confg1;
+	u32 confg1_changes;
+	u32 community;
+	u32 mmio_addr;
+	wchar_t *name;
+	u32 misc;
+};
+
+struct __packed silicon_upd {
+	u64 signature;				/* Offset 0x0100 */
+	u8 revision;				/* Offset 0x0108 */
+	u8 unused3[7];				/* Offset 0x0109 */
+	u8 sdcard_mode;				/* Offset 0x0110 */
+	u8 enable_hsuart0;			/* Offset 0x0111 */
+	u8 enable_hsuart1;			/* Offset 0x0112 */
+	u8 enable_azalia;			/* Offset 0x0113 */
+	struct azalia_config *azalia_cfg_ptr;	/* Offset 0x0114 */
+	u8 enable_sata;				/* Offset 0x0118 */
+	u8 enable_xhci;				/* Offset 0x0119 */
+	u8 lpe_mode;				/* Offset 0x011a */
+	u8 enable_dma0;				/* Offset 0x011b */
+	u8 enable_dma1;				/* Offset 0x011c */
+	u8 enable_i2c0;				/* Offset 0x011d */
+	u8 enable_i2c1;				/* Offset 0x011e */
+	u8 enable_i2c2;				/* Offset 0x011f */
+	u8 enable_i2c3;				/* Offset 0x0120 */
+	u8 enable_i2c4;				/* Offset 0x0121 */
+	u8 enable_i2c5;				/* Offset 0x0122 */
+	u8 enable_i2c6;				/* Offset 0x0123 */
+	u32 graphics_config_ptr;		/* Offset 0x0124 */
+	struct gpio_family *gpio_familiy_ptr;	/* Offset 0x0128 */
+	struct gpio_pad *gpio_pad_ptr;		/* Offset 0x012c */
+	u8 disable_punit_pwr_config;		/* Offset 0x0130 */
+	u8 chv_svid_config;			/* Offset 0x0131 */
+	u8 disable_dptf;			/* Offset 0x0132 */
+	u8 emmc_mode;				/* Offset 0x0133 */
+	u8 usb3_clk_ssc;			/* Offset 0x0134 */
+	u8 disp_clk_ssc;			/* Offset 0x0135 */
+	u8 sata_clk_ssc;			/* Offset 0x0136 */
+	u8 usb2_port0_pe_txi_set;		/* Offset 0x0137 */
+	u8 usb2_port0_txi_set;			/* Offset 0x0138 */
+	u8 usb2_port0_tx_emphasis_en;		/* Offset 0x0139 */
+	u8 usb2_port0_tx_pe_half;		/* Offset 0x013a */
+	u8 usb2_port1_pe_txi_set;		/* Offset 0x013b */
+	u8 usb2_port1_txi_set;			/* Offset 0x013c */
+	u8 usb2_port1_tx_emphasis_en;		/* Offset 0x013d */
+	u8 usb2_port1_tx_pe_half;		/* Offset 0x013e */
+	u8 usb2_port2_pe_txi_set;		/* Offset 0x013f */
+	u8 usb2_port2_txi_set;			/* Offset 0x0140 */
+	u8 usb2_port2_tx_emphasis_en;		/* Offset 0x0141 */
+	u8 usb2_port2_tx_pe_half;		/* Offset 0x0142 */
+	u8 usb2_port3_pe_txi_set;		/* Offset 0x0143 */
+	u8 usb2_port3_txi_set;			/* Offset 0x0144 */
+	u8 usb2_port3_tx_emphasis_en;		/* Offset 0x0145 */
+	u8 usb2_port3_tx_pe_half;		/* Offset 0x0146 */
+	u8 usb2_port4_pe_txi_set;		/* Offset 0x0147 */
+	u8 usb2_port4_txi_set;			/* Offset 0x0148 */
+	u8 usb2_port4_tx_emphasis_en;		/* Offset 0x0149 */
+	u8 usb2_port4_tx_pe_half;		/* Offset 0x014a */
+	u8 usb3_lane0_ow2tap_gen2_deemph3p5;	/* Offset 0x014b */
+	u8 usb3_lane1_ow2tap_gen2_deemph3p5;	/* Offset 0x014c */
+	u8 usb3_lane2_ow2tap_gen2_deemph3p5;	/* Offset 0x014d */
+	u8 usb3_lane3_ow2tap_gen2_deemph3p5;	/* Offset 0x014e */
+	u8 sata_speed;				/* Offset 0x014f */
+	u8 usb_ssic_port;			/* Offset 0x0150 */
+	u8 usb_hsic_port;			/* Offset 0x0151 */
+	u8 pcie_rootport_speed;			/* Offset 0x0152 */
+	u8 enable_ssic;				/* Offset 0x0153 */
+	u32 logo_ptr;				/* Offset 0x0154 */
+	u32 logo_size;				/* Offset 0x0158 */
+	u8 rtc_lock;				/* Offset 0x015c */
+	u8 pmic_i2c_bus;			/* Offset 0x015d */
+	u8 enable_isp;				/* Offset 0x015e */
+	u8 isp_pci_dev_config;			/* Offset 0x015f */
+	u8 turbo_mode;				/* Offset 0x0160 */
+	u8 pnp_settings;			/* Offset 0x0161 */
+	u8 sd_detect_chk;			/* Offset 0x0162 */
+	u8 reserved[411];			/* Offset 0x0163 */
+};
+
+#define MEMORY_UPD_ID	0x244450554d454d24	/* '$MEMUPD$' */
+#define SILICON_UPD_ID	0x244450555f495324	/* '$SI_UPD$' */
+
+struct __packed upd_region {
+	u64 signature;				/* Offset 0x0000 */
+	u8 revision;				/* Offset 0x0008 */
+	u8 unused0[7];				/* Offset 0x0009 */
+	u32 memory_upd_offset;			/* Offset 0x0010 */
+	u32 silicon_upd_offset;			/* Offset 0x0014 */
+	u64 unused1;				/* Offset 0x0018 */
+	struct memory_upd memory_upd;		/* Offset 0x0020 */
+	struct silicon_upd silicon_upd;		/* Offset 0x0100 */
+	u16 terminator;				/* Offset 0x02fe */
+};
+
+#define VPD_IMAGE_ID	0x2450534657534224	/* '$BSWFSP$' */
+
+struct __packed vpd_region {
+	u64 sign;				/* Offset 0x0000 */
+	u32 img_rev;				/* Offset 0x0008 */
+	u32 upd_offset;				/* Offset 0x000c */
+};
+
+#endif /* __FSP_VPD_H__ */
diff --git a/arch/x86/include/asm/arch-braswell/gpio.h b/arch/x86/include/asm/arch-braswell/gpio.h
new file mode 100644
index 0000000..ff82a27
--- /dev/null
+++ b/arch/x86/include/asm/arch-braswell/gpio.h
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * From coreboot src/soc/intel/braswell/include/soc/gpio.h
+ */
+
+#ifndef _BRASWELL_GPIO_H_
+#define _BRASWELL_GPIO_H_
+
+#include <asm/arch/iomap.h>
+
+#define NA		0xff
+#define LOW		0
+#define HIGH		1
+#define MASK_WAKE	0
+#define UNMASK_WAKE	1
+
+enum mode_list {
+	M0,
+	M1,
+	M2,
+	M3,
+	M4,
+	M5,
+	M6,
+	M7,
+	M8,
+	M9,
+	M10,
+	M11,
+	M12,
+	M13,
+};
+
+enum int_select {
+	L0,
+	L1,
+	L2,
+	L3,
+	L4,
+	L5,
+	L6,
+	L7,
+	L8,
+	L9,
+	L10,
+	L11,
+	L12,
+	L13,
+	L14,
+	L15,
+};
+
+enum int_type {
+	INT_DIS,
+	TRIG_EDGE_LOW,
+	TRIG_EDGE_HIGH,
+	TRIG_EDGE_BOTH,
+	TRIG_LEVEL,
+};
+
+enum glitch_cfg {
+	GLITCH_DISABLE,
+	EN_EDGE_DETECT,
+	EN_RX_DATA,
+	EN_EDGE_RX_DATA,
+};
+
+enum mask {
+	MASKABLE,
+	NON_MASKABLE,
+};
+
+enum community {
+	SOUTHWEST = 0x0000,
+	NORTH = 0x8000,
+	EAST = 0x10000,
+	SOUTHEAST = 0x18000,
+	VIRTUAL = 0x20000,
+};
+
+enum gpe_config {
+	GPE,
+	SMI,
+	SCI,
+};
+
+enum inv_rx_tx {
+	NO_INVERSION = 0,
+	INV_RX_ENABLE = 1,
+	INV_TX_ENABLE = 2,
+	INV_RX_TX_ENABLE = 3,
+	INV_RX_DATA = 4,
+	INV_TX_DATA = 8,
+};
+
+enum gpio_en {
+	NATIVE = 0xff,
+	GPIO = 0,	/* Native, no need to set PAD_VALUE */
+	GPO = 1,	/* GPO, output only in PAD_VALUE */
+	GPI = 2,	/* GPI, input only in PAD_VALUE */
+	HI_Z = 3,
+	NA_GPO = 0,
+};
+
+enum gpo_d4 {
+	LO,
+	HI,
+};
+
+enum gpio_func_num {
+	F0,
+	F1,
+	F2,
+	F3,
+};
+
+enum int_capable {
+	_CAP = 1,
+	_NOT_CAP = 0
+};
+
+enum pull_type {
+	P_NONE  = 0,	/* Pull None */
+	P_20K_L = 1,	/* Pull Down 20K */
+	P_5K_L  = 2,	/* Pull Down  5K */
+	P_1K_L  = 4,	/* Pull Down  1K */
+	P_20K_H = 9,	/* Pull Up 20K */
+	P_5K_H  = 10,	/* Pull Up  5K */
+	P_1K_H  = 12	/* Pull Up  1K */
+};
+
+enum park_mode_enb {
+	DISABLE,	/* Disable */
+	ENABLE,		/* Enable */
+};
+
+enum voltage {
+	VOLT_3_3,	/* Working on 3.3 Volts */
+	VOLT_1_8,	/* Working on 1.8 Volts */
+};
+
+enum hs_mode {
+	DISABLE_HS,	/* Disable high speed mode */
+	ENABLE_HS,	/* Enable high speed mode */
+};
+
+enum odt_up_dn {
+	PULL_UP,	/* On Die Termination Up */
+	PULL_DOWN,	/* On Die Termination Down */
+};
+
+enum odt_en {
+	DISABLE_OD,	/* On Die Termination Disable */
+	ENABLE_OD,	/* On Die Termination Enable */
+};
+
+enum bit {
+	ONE_BIT = 1,
+	TWO_BIT = 3,
+	THREE_BIT = 7,
+	FOUR_BIT = 15,
+	FIVE_BIT = 31,
+	SIX_BIT = 63,
+	SEVEN_BIT = 127,
+	EIGHT_BIT = 255
+};
+
+#define TERMINATOR	0xffffffff
+
+#define GPIO_FAMILY_CONF(family_name, park_mode, hysctl, vp18_mode, hs_mode, \
+	odt_up_dn, odt_en, curr_src_str, rcomp, family_no, community_offset) { \
+	.confg = ((((park_mode) != NA) ? park_mode << 26 : 0) | \
+		  (((hysctl) != NA) ? hysctl << 24 : 0) | \
+		  (((vp18_mode) != NA) ? vp18_mode << 21 : 0) | \
+		  (((hs_mode) != NA) ? hs_mode << 19 : 0) | \
+		  (((odt_up_dn) != NA) ? odt_up_dn << 18 : 0) | \
+		  (((odt_en) != NA) ? odt_en << 17 : 0) | \
+		  (curr_src_str)), \
+	.confg_changes = ((((park_mode) != NA) ? ONE_BIT << 26 : 0) | \
+			  (((hysctl) != NA) ? TWO_BIT << 24 : 0) | \
+			  (((vp18_mode) != NA) ? ONE_BIT  << 21 : 0) | \
+			  (((hs_mode) != NA) ? ONE_BIT << 19 : 0) | \
+			  (((odt_up_dn) != NA) ? ONE_BIT << 18 : 0) | \
+			  (((odt_en) != NA) ? ONE_BIT << 17 : 0) | \
+			  (THREE_BIT)), \
+	.misc = ((rcomp == ENABLE) ? 1 : 0) , \
+	.mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
+		     ((family_no != NA) ? (IO_BASE_ADDRESS + community_offset +\
+		     (0x80 * family_no) + 0x1080) : 0) , \
+	.name = 0 \
+}
+
+#define GPIO_PAD_CONF(pad_name, mode_select, mode, gpio_config, gpio_state, \
+	gpio_light_mode, int_type, int_sel, term, open_drain, current_source,\
+	int_mask, glitch, inv_rx_tx, wake_mask, wake_mask_bit, gpe, \
+	mmio_offset, community_offset) { \
+	.confg0 = ((((int_sel) != NA) ? (int_sel << 28) : 0) | \
+		   (((glitch) != NA) ? (glitch << 26) : 0) | \
+		   (((term) != NA) ? (term << 20) : 0) | \
+		   (((mode_select) == GPIO) ? ((mode << 16) | (1 << 15)) : \
+		    ((mode << 16))) | \
+		   (((gpio_config) != NA) ? (gpio_config << 8) : 0) | \
+		   (((gpio_light_mode) != NA) ? (gpio_light_mode << 7) : 0) | \
+		   (((gpio_state) == HIGH) ? 2 : 0)), \
+	.confg0_changes = ((((int_sel) != NA) ? (FOUR_BIT << 28) : 0) | \
+			   (((glitch) != NA) ? (TWO_BIT << 26) : 0) | \
+			   (((term) != NA) ? (FOUR_BIT << 20) : 0) | \
+			   (FIVE_BIT << 15) | \
+			   (((gpio_config) != NA) ? (THREE_BIT << 8) : 0) | \
+			   (((gpio_light_mode) != NA) ? (ONE_BIT << 7) : 0) | \
+			   (((gpio_state) != NA) ? ONE_BIT << 1 : 0)), \
+	.confg1  = ((((current_source) != NA) ? (current_source << 27) : 0) | \
+		    (((inv_rx_tx) != NA) ? inv_rx_tx << 4 : 0) | \
+		    (((open_drain) != NA) ? open_drain << 3 : 0) | \
+		    (((int_type) != NA) ? int_type : 0)), \
+	.confg1_changes = ((((current_source) != NA) ? (ONE_BIT << 27) : 0) | \
+			   (((inv_rx_tx) != NA) ? FOUR_BIT << 4 : 0) | \
+			   (((open_drain) != NA) ? ONE_BIT << 3 : 0) | \
+			   (((int_type) != NA) ? THREE_BIT : 0)), \
+	.community = community_offset, \
+	.mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
+		     ((mmio_offset != NA) ? (IO_BASE_ADDRESS + \
+		      community_offset + mmio_offset) : 0), \
+	.name = 0, \
+	.misc = ((((gpe) != NA) ? (gpe << 0) : 0) | \
+		 (((wake_mask) != NA) ? (wake_mask << 2) : 0) | \
+		 (((int_mask) != NA) ? (int_mask << 3) : 0)) | \
+		 (((wake_mask_bit) != NA) ? (wake_mask_bit << 4) : (NA << 4)) \
+}
+
+#endif /* _BRASWELL_GPIO_H_ */
-- 
2.9.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 12/13] x86: braswell: Disable PUNIT power configuration for B0 stepping
  2017-08-16  5:41 [U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support Bin Meng
                   ` (10 preceding siblings ...)
  2017-08-16  5:42 ` [U-Boot] [PATCH 11/13] x86: braswell: Add FSP configuration Bin Meng
@ 2017-08-16  5:42 ` Bin Meng
  2017-08-26 13:39   ` Simon Glass
  2017-08-16  5:42 ` [U-Boot] [PATCH 13/13] x86: Support Intel Cherry Hill board Bin Meng
  12 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-16  5:42 UTC (permalink / raw
  To: u-boot

FSP's built-in UPD configuration enables PUNIT power configuration,
but on B0 stepping, this causes CPU hangs in fsp_init(). Disable it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/braswell/fsp_configs.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/x86/cpu/braswell/fsp_configs.c b/arch/x86/cpu/braswell/fsp_configs.c
index d984519..249f851 100644
--- a/arch/x86/cpu/braswell/fsp_configs.c
+++ b/arch/x86/cpu/braswell/fsp_configs.c
@@ -139,6 +139,12 @@ void update_fsp_configs(struct fsp_config_data *config,
 #endif
 	update_fsp_gpio_configs(&silicon_upd->gpio_familiy_ptr,
 				&silicon_upd->gpio_pad_ptr);
+	/*
+	 * For Braswell B0 stepping, disable_punit_pwr_config must be set to 1
+	 * otherwise it just hangs in fsp_init().
+	 */
+	if (gd->arch.x86_mask == 2)
+		silicon_upd->disable_punit_pwr_config = 1;
 	silicon_upd->emmc_mode = fdtdec_get_int(blob, node,
 		"fsp,emmc-mode", EMMC_MODE_PCI);
 	silicon_upd->sata_speed = fdtdec_get_int(blob, node,
-- 
2.9.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 13/13] x86: Support Intel Cherry Hill board
  2017-08-16  5:41 [U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support Bin Meng
                   ` (11 preceding siblings ...)
  2017-08-16  5:42 ` [U-Boot] [PATCH 12/13] x86: braswell: Disable PUNIT power configuration for B0 stepping Bin Meng
@ 2017-08-16  5:42 ` Bin Meng
  2017-08-26 13:39   ` Simon Glass
  12 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-16  5:42 UTC (permalink / raw
  To: u-boot

This adds support to Intel Cherry Hill board, a board based on
Intel Braswell SoC. The following devices are validated:

- serial port as the serial console
- on-board Realtek 8169 ethernet controller
- SATA AHCI controller
- EMMC/SDHC controller
- USB 3.0 xHCI controller
- PCIe x1 slot with a graphics card
- ICH SPI controller with an 8MB Macronix SPI flash
- Integrated graphics device as the video console

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

 arch/x86/dts/Makefile               |   1 +
 arch/x86/dts/cherryhill.dts         | 215 +++++++++++++
 board/intel/Kconfig                 |  10 +
 board/intel/cherryhill/Kconfig      |  25 ++
 board/intel/cherryhill/MAINTAINERS  |   6 +
 board/intel/cherryhill/Makefile     |   7 +
 board/intel/cherryhill/cherryhill.c | 596 ++++++++++++++++++++++++++++++++++++
 board/intel/cherryhill/start.S      |   9 +
 configs/cherryhill_defconfig        |  36 +++
 doc/README.x86                      |  30 ++
 include/configs/cherryhill.h        |  22 ++
 11 files changed, 957 insertions(+)
 create mode 100644 arch/x86/dts/cherryhill.dts
 create mode 100644 board/intel/cherryhill/Kconfig
 create mode 100644 board/intel/cherryhill/MAINTAINERS
 create mode 100644 board/intel/cherryhill/Makefile
 create mode 100644 board/intel/cherryhill/cherryhill.c
 create mode 100644 board/intel/cherryhill/start.S
 create mode 100644 configs/cherryhill_defconfig
 create mode 100644 include/configs/cherryhill.h

diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 6589495..6d0c4b6 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -3,6 +3,7 @@
 #
 
 dtb-y += bayleybay.dtb \
+	cherryhill.dtb \
 	chromebook_link.dtb \
 	chromebox_panther.dtb \
 	chromebook_samus.dtb \
diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts
new file mode 100644
index 0000000..1ccb605
--- /dev/null
+++ b/arch/x86/dts/cherryhill.dts
@@ -0,0 +1,215 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include <asm/arch-braswell/fsp/fsp_configs.h>
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+	model = "Intel Cherry Hill";
+	compatible = "intel,cherryhill", "intel,braswell";
+
+	aliases {
+		serial0 = &serial;
+		spi0 = &spi;
+	};
+
+	config {
+		silent_console = <0>;
+	};
+
+	chosen {
+		stdout-path = "/serial";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "intel,braswell-cpu";
+			reg = <0>;
+			intel,apic-id = <0>;
+		};
+
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "intel,braswell-cpu";
+			reg = <1>;
+			intel,apic-id = <2>;
+		};
+
+		cpu at 2 {
+			device_type = "cpu";
+			compatible = "intel,braswell-cpu";
+			reg = <2>;
+			intel,apic-id = <4>;
+		};
+
+		cpu at 3 {
+			device_type = "cpu";
+			compatible = "intel,braswell-cpu";
+			reg = <3>;
+			intel,apic-id = <6>;
+		};
+	};
+
+	pci {
+		compatible = "pci-x86";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
+			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
+			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+		pch at 1f,0 {
+			reg = <0x0000f800 0 0 0 0>;
+			compatible = "intel,pch9";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			irq-router {
+				compatible = "intel,irq-router";
+				intel,pirq-config = "ibase";
+				intel,ibase-offset = <0x50>;
+				intel,pirq-link = <8 8>;
+				intel,pirq-mask = <0xdee0>;
+				intel,pirq-routing = <
+					/* Braswell PCI devices */
+					PCI_BDF(0, 2, 0) INTA PIRQA
+					PCI_BDF(0, 3, 0) INTA PIRQA
+					PCI_BDF(0, 11, 0) INTA PIRQA
+					PCI_BDF(0, 16, 0) INTA PIRQA
+					PCI_BDF(0, 17, 0) INTA PIRQA
+					PCI_BDF(0, 18, 0) INTA PIRQA
+					PCI_BDF(0, 19, 0) INTA PIRQA
+					PCI_BDF(0, 20, 0) INTA PIRQA
+					PCI_BDF(0, 21, 0) INTA PIRQA
+					PCI_BDF(0, 24, 0) INTA PIRQA
+					PCI_BDF(0, 24, 1) INTC PIRQC
+					PCI_BDF(0, 24, 2) INTD PIRQD
+					PCI_BDF(0, 24, 3) INTB PIRQB
+					PCI_BDF(0, 24, 4) INTA PIRQA
+					PCI_BDF(0, 24, 5) INTC PIRQC
+					PCI_BDF(0, 24, 6) INTD PIRQD
+					PCI_BDF(0, 24, 7) INTB PIRQB
+					PCI_BDF(0, 26, 0) INTA PIRQA
+					PCI_BDF(0, 27, 0) INTA PIRQA
+					PCI_BDF(0, 28, 0) INTA PIRQA
+					PCI_BDF(0, 28, 1) INTB PIRQB
+					PCI_BDF(0, 28, 2) INTC PIRQC
+					PCI_BDF(0, 28, 3) INTD PIRQD
+					PCI_BDF(0, 30, 0) INTA PIRQA
+					PCI_BDF(0, 30, 3) INTA PIRQA
+					PCI_BDF(0, 30, 4) INTA PIRQA
+					PCI_BDF(0, 31, 0) INTB PIRQB
+					PCI_BDF(0, 31, 3) INTB PIRQB
+
+					/*
+					 * PCIe root ports downstream
+					 * interrupts
+					 */
+					PCI_BDF(1, 0, 0) INTA PIRQA
+					PCI_BDF(1, 0, 0) INTB PIRQB
+					PCI_BDF(1, 0, 0) INTC PIRQC
+					PCI_BDF(1, 0, 0) INTD PIRQD
+					PCI_BDF(2, 0, 0) INTA PIRQB
+					PCI_BDF(2, 0, 0) INTB PIRQC
+					PCI_BDF(2, 0, 0) INTC PIRQD
+					PCI_BDF(2, 0, 0) INTD PIRQA
+					PCI_BDF(3, 0, 0) INTA PIRQC
+					PCI_BDF(3, 0, 0) INTB PIRQD
+					PCI_BDF(3, 0, 0) INTC PIRQA
+					PCI_BDF(3, 0, 0) INTD PIRQB
+					PCI_BDF(4, 0, 0) INTA PIRQD
+					PCI_BDF(4, 0, 0) INTB PIRQA
+					PCI_BDF(4, 0, 0) INTC PIRQB
+					PCI_BDF(4, 0, 0) INTD PIRQC
+				>;
+			};
+
+			spi: spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich9-spi";
+
+				spi-flash at 0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					reg = <0>;
+					compatible = "macronix,mx25u6435f", "spi-flash";
+					memory-map = <0xff800000 0x00800000>;
+					rw-mrc-cache {
+						label = "rw-mrc-cache";
+						reg = <0x005e0000 0x00010000>;
+					};
+				};
+			};
+		};
+	};
+
+	fsp {
+		compatible = "intel,braswell-fsp";
+		fsp,memory-upd {
+			compatible = "intel,braswell-fsp-memory";
+			fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_4MB>;
+			fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
+			fsp,mrc-init-spd-addr1 = <0xa0>;
+			fsp,mrc-init-spd-addr2 = <0xa2>;
+			fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_32MB>;
+			fsp,aperture-size = <APERTURE_SIZE_256MB>;
+			fsp,gtt-size = <GTT_SIZE_1MB>;
+			fsp,enable-dvfs;
+			fsp,memory-type = <DRAM_TYPE_DDR3>;
+		};
+		fsp,silicon-upd {
+			compatible = "intel,braswell-fsp-silicon";
+			fsp,sdcard-mode = <SDCARD_MODE_PCI>;
+			fsp,enable-hsuart1;
+			fsp,enable-sata;
+			fsp,enable-xhci;
+			fsp,lpe-mode = <LPE_MODE_PCI>;
+			fsp,enable-dma0;
+			fsp,enable-dma1;
+			fsp,enable-i2c0;
+			fsp,enable-i2c1;
+			fsp,enable-i2c2;
+			fsp,enable-i2c3;
+			fsp,enable-i2c4;
+			fsp,enable-i2c5;
+			fsp,enable-i2c6;
+			fsp,emmc-mode = <EMMC_MODE_PCI>;
+			fsp,sata-speed = <SATA_SPEED_GEN3>;
+			fsp,pmic-i2c-bus = <0>;
+			fsp,enable-isp;
+			fsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>;
+			fsp,turbo-mode;
+			fsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>;
+			fsp,sd-detect-chk;
+		};
+	};
+
+	microcode {
+		update at 0 {
+#include "microcode/m01406c2220.dtsi"
+		};
+		update at 1 {
+#include "microcode/m01406c3363.dtsi"
+		};
+		update at 2 {
+#include "microcode/m01406c440a.dtsi"
+		};
+	};
+
+};
diff --git a/board/intel/Kconfig b/board/intel/Kconfig
index d7d950e..4ebf808 100644
--- a/board/intel/Kconfig
+++ b/board/intel/Kconfig
@@ -18,6 +18,15 @@ config TARGET_BAYLEYBAY
 	  4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC,
 	  PCIe and some other sensor interfaces.
 
+config TARGET_CHERRYHILL
+	bool "Cherry Hill"
+	help
+	  This is the Intel Cherry Hill Customer Reference Board. It is in a
+	  mini-ITX form factor containing the Intel Braswell SoC, which has
+	  a 64-bit quad-core, single-thread, Intel Atom processor, along with
+	  serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe,
+	  some GPIOs, one HDMI and two DP video out.
+
 config TARGET_COUGARCANYON2
 	bool "Cougar Canyon 2"
 	help
@@ -69,6 +78,7 @@ config TARGET_MINNOWMAX
 endchoice
 
 source "board/intel/bayleybay/Kconfig"
+source "board/intel/cherryhill/Kconfig"
 source "board/intel/cougarcanyon2/Kconfig"
 source "board/intel/crownbay/Kconfig"
 source "board/intel/edison/Kconfig"
diff --git a/board/intel/cherryhill/Kconfig b/board/intel/cherryhill/Kconfig
new file mode 100644
index 0000000..a4fa004
--- /dev/null
+++ b/board/intel/cherryhill/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_CHERRYHILL
+
+config SYS_BOARD
+	default "cherryhill"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "braswell"
+
+config SYS_CONFIG_NAME
+	default "cherryhill"
+
+config SYS_TEXT_BASE
+	default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_BRASWELL
+	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_MACRONIX
+
+endif
diff --git a/board/intel/cherryhill/MAINTAINERS b/board/intel/cherryhill/MAINTAINERS
new file mode 100644
index 0000000..6e90f64
--- /dev/null
+++ b/board/intel/cherryhill/MAINTAINERS
@@ -0,0 +1,6 @@
+INTEL CHERRYHILL BOARD
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/intel/cherryhill/
+F:	include/configs/cherryhill.h
+F:	configs/cherryhill_defconfig
diff --git a/board/intel/cherryhill/Makefile b/board/intel/cherryhill/Makefile
new file mode 100644
index 0000000..0dbb055
--- /dev/null
+++ b/board/intel/cherryhill/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= cherryhill.o start.o
diff --git a/board/intel/cherryhill/cherryhill.c b/board/intel/cherryhill/cherryhill.c
new file mode 100644
index 0000000..d86dc97
--- /dev/null
+++ b/board/intel/cherryhill/cherryhill.c
@@ -0,0 +1,596 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/fsp/fsp_support.h>
+
+static const struct gpio_family gpio_family[] = {
+	GPIO_FAMILY_CONF("SOUTHEAST_2_hshvfamily_2x3_rcomp_7_0", NA, 0,
+			 VOLT_1_8, NA, NA, NA, 0, ENABLE, 2, SOUTHEAST),
+
+	/* end of the table */
+	GPIO_FAMILY_CONF("GPIO FAMILY TABLE END", NA, 0,
+			 VOLT_1_8, NA, NA, NA, 0, DISABLE, 0, TERMINATOR),
+};
+
+static const struct gpio_pad gpio_pad[] = {
+	GPIO_PAD_CONF("N37: CX_PRDY_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 29, NA, 0x4c38, NORTH),
+	GPIO_PAD_CONF("N35: CX_PRDY_B_2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 27, NA, 0x4c28, NORTH),
+	GPIO_PAD_CONF("N39: CX_PREQ_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 20, NA, 0x4858, NORTH),
+	GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 37, NA, 0x5018, NORTH),
+	GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 42, NA, 0x5040, NORTH),
+	GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 35, NA, 0x5008, NORTH),
+	GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 40, NA, 0x5030, NORTH),
+	GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 45, NA, 0x5058, NORTH),
+	GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 34, NA, 0x5000, NORTH),
+	GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 38, NA, 0x5020, NORTH),
+	GPIO_PAD_CONF("N54: GP_CAMERASB07", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 43, NA, 0x5048, NORTH),
+	GPIO_PAD_CONF("N47: GP_CAMERASB08", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 36, NA, 0x5010, NORTH),
+	GPIO_PAD_CONF("N52: GP_CAMERASB09", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 41, NA, 0x5038, NORTH),
+	GPIO_PAD_CONF("N50: GP_CAMERASB10", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 39, NA, 0x5028, NORTH),
+	GPIO_PAD_CONF("N55: GP_CAMERASB11", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 44, NA, 0x5050, NORTH),
+	GPIO_PAD_CONF("N00: GPIO_DFX0", NATIVE, M5, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 0, NA, 0x4400, NORTH),
+	GPIO_PAD_CONF("N03: GPIO_DFX1", NATIVE, M5, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 3, NA, 0x4418, NORTH),
+	GPIO_PAD_CONF("N07: GPIO_DFX2", NATIVE, M5, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 2, NA, 0x4438, NORTH),
+	GPIO_PAD_CONF("N01: GPIO_DFX3", NATIVE, M5, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 1, NA, 0x4408, NORTH),
+	GPIO_PAD_CONF("N05: GPIO_DFX4", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 5, NA, 0x4428, NORTH),
+	GPIO_PAD_CONF("N04: GPIO_DFX5", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 4, NA, 0x4420, NORTH),
+	GPIO_PAD_CONF("N08: GPIO_DFX6", NATIVE, M8, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 8, NA, 0x4440, NORTH),
+	GPIO_PAD_CONF("N02: GPIO_DFX7", GPIO, M1, GPO, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 2, NA, 0x4410, NORTH),
+	GPIO_PAD_CONF("N15: GPIO_SUS0", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 9 , NA, 0x4800, NORTH),
+	GPIO_PAD_CONF("N19: GPIO_SUS1", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 13, NA, 0x4820, NORTH),
+	GPIO_PAD_CONF("N24: GPIO_SUS2", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 18, NA, 0x4848, NORTH),
+	GPIO_PAD_CONF("N17: GPIO_SUS3", NATIVE, M6, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 11, NA, 0x4810, NORTH),
+	GPIO_PAD_CONF("N22: GPIO_SUS4", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 16, NA, 0x4838, NORTH),
+	GPIO_PAD_CONF("N20: GPIO_SUS5", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 14, NA, 0x4828, NORTH),
+	GPIO_PAD_CONF("N25: GPIO_SUS6", GPIO, M1, GPI, NA, NA,
+		      TRIG_EDGE_LOW, L9, NA, NA, NA, NON_MASKABLE,
+		      EN_EDGE_RX_DATA, NO_INVERSION,
+		      NA, 19, SCI, 0x4850, NORTH),
+	GPIO_PAD_CONF("N18: GPIO_SUS7", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 12, SMI, 0x4818, NORTH),
+	GPIO_PAD_CONF("N71: HV_DDI0_DDC_SCL", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 57, NA, 0x5458, NORTH),
+	GPIO_PAD_CONF("N66: HV_DDI0_DDC_SDA", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 52, NA, 0x5430, NORTH),
+	GPIO_PAD_CONF("N61: HV_DDI0_HPD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 47, NA, 0x5408, NORTH),
+	GPIO_PAD_CONF("N64: HV_DDI1_HPD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 50, NA, 0x5420, NORTH),
+	GPIO_PAD_CONF("N67: HV_DDI2_DDC_SCL", NATIVE, M3, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 53, NA, 0x5438, NORTH),
+	GPIO_PAD_CONF("N62: HV_DDI2_DDC_SDA", NATIVE, M3, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 48, NA, 0x5410, NORTH),
+	GPIO_PAD_CONF("N68: HV_DDI2_HPD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 54, NA, 0x5440, NORTH),
+	GPIO_PAD_CONF("N65: PANEL0_BKLTCTL", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 51, NA, 0x5428, NORTH),
+	GPIO_PAD_CONF("N60: PANEL0_BKLTEN", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 46, NA, 0x5400, NORTH),
+	GPIO_PAD_CONF("N72: PANEL0_VDDEN", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 58, NA, 0x5460, NORTH),
+	GPIO_PAD_CONF("N63: PANEL1_BKLTCTL", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 49, NA, 0x5418, NORTH),
+	GPIO_PAD_CONF("N70: PANEL1_BKLTEN", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 56, NA, 0x5450, NORTH),
+	GPIO_PAD_CONF("N69: PANEL1_VDDEN", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 55, NA, 0x5448, NORTH),
+	GPIO_PAD_CONF("N32: PROCHOT_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 24, NA, 0x4c10, NORTH),
+	GPIO_PAD_CONF("N16: SEC_GPIO_SUS10", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 10, NA, 0x4808, NORTH),
+	GPIO_PAD_CONF("N21: SEC_GPIO_SUS11", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 15, NA, 0x4830, NORTH),
+	GPIO_PAD_CONF("N23: SEC_GPIO_SUS8", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 17, NA, 0x4840, NORTH),
+	GPIO_PAD_CONF("N27: SEC_GPIO_SUS9", GPIO, M1, GPI, LOW, NA,
+		      TRIG_LEVEL, L15, NA, NA, NA, NON_MASKABLE,
+		      EN_RX_DATA, INV_RX_DATA,
+		      NA, 21, SCI, 0x4860, NORTH),
+	GPIO_PAD_CONF("N31: TCK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 23, NA, 0x4c08, NORTH),
+	GPIO_PAD_CONF("N41: TDI", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 33, NA, 0x4c58, NORTH),
+	GPIO_PAD_CONF("N39: TDO", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 31, NA, 0x4c48, NORTH),
+	GPIO_PAD_CONF("N36: TDO_2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 28, NA, 0x4c30, NORTH),
+	GPIO_PAD_CONF("N34: TMS", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 26, NA, 0x4c20, NORTH),
+	GPIO_PAD_CONF("N30: TRST_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 22, NA, 0x4c00, NORTH),
+
+	GPIO_PAD_CONF("E21: MF_ISH_GPIO_0", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 18, NA, 0x4830, EAST),
+	GPIO_PAD_CONF("E18: MF_ISH_GPIO_1", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 15, NA, 0x4818, EAST),
+	GPIO_PAD_CONF("E24: MF_ISH_GPIO_2", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 21, NA, 0x4848, EAST),
+	GPIO_PAD_CONF("E15: MF_ISH_GPIO_3", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 12, NA, 0x4800, EAST),
+	GPIO_PAD_CONF("E22: MF_ISH_GPIO_4", GPIO, M1, GPI, NA, NA,
+		      NA, L0, NA, NA, NA, NON_MASKABLE, NA, NO_INVERSION,
+		      NA, 19, NA, 0x4838, EAST),
+	GPIO_PAD_CONF("E19: MF_ISH_GPIO_5", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 16, NA, 0x4820, EAST),
+	GPIO_PAD_CONF("E25: MF_ISH_GPIO_6", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 22, NA, 0x4850, EAST),
+	GPIO_PAD_CONF("E16: MF_ISH_GPIO_7", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 13, NA, 0x4808, EAST),
+	GPIO_PAD_CONF("E23: MF_ISH_GPIO_8", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 20, NA, 0x4840, EAST),
+	GPIO_PAD_CONF("E20: MF_ISH_GPIO_9", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 17, NA, 0x4828, EAST),
+	GPIO_PAD_CONF("E26: MF_ISH_I2C1_SDA", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 23, NA, 0x4858, EAST),
+	GPIO_PAD_CONF("E17: MF_ISH_I2C1_SCL", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 14, NA, 0x4810, EAST),
+	GPIO_PAD_CONF("E04: PMU_AC_PRESENT", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 4, NA, 0x4420, EAST),
+	GPIO_PAD_CONF("E01: PMU_BATLOW_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 1, NA, 0x4408, EAST),
+	GPIO_PAD_CONF("E05: PMU_PLTRST_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 5, NA, 0x4428, EAST),
+	GPIO_PAD_CONF("E07: PMU_SLP_LAN_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 7, NA, 0x4438, EAST),
+	GPIO_PAD_CONF("E03: PMU_SLP_S0IX_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 3, NA, 0x4418, EAST),
+	GPIO_PAD_CONF("E00: PMU_SLP_S3_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 0, NA, 0x4400, EAST),
+	GPIO_PAD_CONF("E09: PMU_SLP_S4_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 9, NA, 0x4448, EAST),
+	GPIO_PAD_CONF("E06: PMU_SUSCLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 6, NA, 0x4430, EAST),
+	GPIO_PAD_CONF("E10: PMU_WAKE_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 10, NA, 0x4450, EAST),
+	GPIO_PAD_CONF("E11: PMU_WAKE_LAN_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 11, NA, 0x4458, EAST),
+	GPIO_PAD_CONF("E02: SUS_STAT_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 2, NA, 0x4410, EAST),
+
+	GPIO_PAD_CONF("SE16: SDMMC1_CLK", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 9, NA, 0x4808, SOUTHEAST),
+	GPIO_PAD_CONF("SE23: SDMMC1_CMD", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 16, NA, 0x4840, SOUTHEAST),
+	GPIO_PAD_CONF("SE17: SDMMC1_D0", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 10, NA, 0x4810, SOUTHEAST),
+	GPIO_PAD_CONF("SE24: SDMMC1_D1", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 17, NA, 0x4848, SOUTHEAST),
+	GPIO_PAD_CONF("SE20: SDMMC1_D2", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 13, NA, 0x4828, SOUTHEAST),
+	GPIO_PAD_CONF("SE26: SDMMC1_D3_CD_B", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 19, NA, 0x4858, SOUTHEAST),
+	GPIO_PAD_CONF("SE67: MMC1_D4_SD_WE", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 41, NA, 0x5438, SOUTHEAST),
+	GPIO_PAD_CONF("SE65: MMC1_D5", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 39, NA, 0x5428, SOUTHEAST),
+	GPIO_PAD_CONF("SE63: MMC1_D6", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 37, NA, 0x5418, SOUTHEAST),
+	GPIO_PAD_CONF("SE68: MMC1_D7", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 42, NA, 0x5440, SOUTHEAST),
+	GPIO_PAD_CONF("SE69: MMC1_RCLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 43, NA, 0x5448, SOUTHEAST),
+	GPIO_PAD_CONF("SE77: GPIO_ALERT", GPIO, M1, GPI, NA, NA,
+		      TRIG_LEVEL, L2, NA, NA, NA, NON_MASKABLE,
+		      EN_RX_DATA, INV_RX_DATA,
+		      NA, 46, NA, 0x5810, SOUTHEAST),
+	GPIO_PAD_CONF("SE79: ILB_SERIRQ", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 48, NA, 0x5820, SOUTHEAST),
+	GPIO_PAD_CONF("SE51: MF_LPC_CLKOUT0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 32, NA, 0x5030, SOUTHEAST),
+	GPIO_PAD_CONF("SE49: MF_LPC_CLKOUT1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 30, NA, 0x5020, SOUTHEAST),
+	GPIO_PAD_CONF("SE47: MF_LPC_AD0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 28, NA, 0x5010, SOUTHEAST),
+	GPIO_PAD_CONF("SE52: MF_LPC_AD1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 33, NA, 0x5038, SOUTHEAST),
+	GPIO_PAD_CONF("SE45: MF_LPC_AD2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 26, NA, 0x5000, SOUTHEAST),
+	GPIO_PAD_CONF("SE50: MF_LPC_AD3", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 31, NA, 0x5028, SOUTHEAST),
+	GPIO_PAD_CONF("SE46: LPC_CLKRUNB", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 27, NA, 0x5008, SOUTHEAST),
+	GPIO_PAD_CONF("SE48: LPC_FRAMEB", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 29, NA, 0x5018, SOUTHEAST),
+	GPIO_PAD_CONF("SE00: MF_PLT_CLK0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 0, NA, 0x4400, SOUTHEAST),
+	GPIO_PAD_CONF("SE02: MF_PLT_CLK1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 1, NA, 0x4410, SOUTHEAST),
+	GPIO_PAD_CONF("SE07: MF_PLT_CLK2", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 7, NA, 0x4438, SOUTHEAST),
+	GPIO_PAD_CONF("SE04: MF_PLT_CLK3", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 4, NA, 0x4420, SOUTHEAST),
+	GPIO_PAD_CONF("SE03: MF_PLT_CLK4", GPIO, M1, GPO, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 3, NA, 0x4418, SOUTHEAST),
+	GPIO_PAD_CONF("SE06: MF_PLT_CLK5", GPIO, M3, GPO, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 6, NA, 0x4430, SOUTHEAST),
+	GPIO_PAD_CONF("SE83: SUSPWRDNACK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 52, NA, 0x5840, SOUTHEAST),
+	GPIO_PAD_CONF("SE05: PWM0", GPIO, M1, GPO, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 5, NA, 0x4428, SOUTHEAST),
+	GPIO_PAD_CONF("SE01: PWM1", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 1, NA, 0x4408, SOUTHEAST),
+	GPIO_PAD_CONF("SE85: SDMMC3_1P8_EN", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 54, NA, 0x5850, SOUTHEAST),
+	GPIO_PAD_CONF("SE81: SDMMC3_CD_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 50, NA, 0x5830, SOUTHEAST),
+	GPIO_PAD_CONF("SE31: SDMMC3_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 21, NA, 0x4c08, SOUTHEAST),
+	GPIO_PAD_CONF("SE34: SDMMC3_CMD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 24, NA, 0x4c20, SOUTHEAST),
+	GPIO_PAD_CONF("SE35: SDMMC3_D0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 25, NA, 0x4c28, SOUTHEAST),
+	GPIO_PAD_CONF("SE30: SDMMC3_D1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 20, NA, 0x4c00, SOUTHEAST),
+	GPIO_PAD_CONF("SE33: SDMMC3_D2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 23, NA, 0x4c18, SOUTHEAST),
+	GPIO_PAD_CONF("SE32: SDMMC3_D3", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 22, NA, 0x4c10, SOUTHEAST),
+	GPIO_PAD_CONF("SE78: SDMMC3_PWR_EN_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 47, NA, 0x5818, SOUTHEAST),
+	GPIO_PAD_CONF("SE19: SDMMC2_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 12, NA, 0x4820, SOUTHEAST),
+	GPIO_PAD_CONF("SE22: SDMMC2_CMD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 15, NA, 0x4838, SOUTHEAST),
+	GPIO_PAD_CONF("SE25: SDMMC2_D0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 18, NA, 0x4850, SOUTHEAST),
+	GPIO_PAD_CONF("SE18: SDMMC2_D1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 11, NA, 0x4818, SOUTHEAST),
+	GPIO_PAD_CONF("SE21: SDMMC2_D2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 14, NA, 0x4830, SOUTHEAST),
+	GPIO_PAD_CONF("SE15: SDMMC2_D3_CD_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 8, NA, 0x4800, SOUTHEAST),
+	GPIO_PAD_CONF("SE62: SPI1_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 36, NA, 0x5410, SOUTHEAST),
+	GPIO_PAD_CONF("SE61: SPI1_CS0_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 35, NA, 0x5408, SOUTHEAST),
+	GPIO_PAD_CONF("SE66: SPI1_CS1_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 40, NA, 0x5430, SOUTHEAST),
+	GPIO_PAD_CONF("SE60: SPI1_MISO", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 34, NA, 0x5400, SOUTHEAST),
+	GPIO_PAD_CONF("SE64: SPI1_MOSI", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 38, NA, 0x5420, SOUTHEAST),
+	GPIO_PAD_CONF("SE80: USB_OC0_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 49, NA, 0x5828, SOUTHEAST),
+	GPIO_PAD_CONF("SE75: USB_OC1_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 44, NA, 0x5800, SOUTHEAST),
+	GPIO_PAD_CONF("SW02: FST_SPI_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 2, NA, 0x4410, SOUTHWEST),
+	GPIO_PAD_CONF("SW06: FST_SPI_CS0_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 6, NA, 0x4430, SOUTHWEST),
+	GPIO_PAD_CONF("SW04: FST_SPI_CS1_B", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 4, NA, 0x4420, SOUTHWEST),
+	GPIO_PAD_CONF("SW07: FST_SPI_CS2_B", GPIO, M1, GPO, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 7, NA, 0x4438, SOUTHWEST),
+	GPIO_PAD_CONF("SW01: FST_SPI_D0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 1, NA, 0x4408, SOUTHWEST),
+	GPIO_PAD_CONF("SW05: FST_SPI_D1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 5, NA, 0x4428, SOUTHWEST),
+	GPIO_PAD_CONF("SW00: FST_SPI_D2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 0, NA, 0x4400, SOUTHWEST),
+	GPIO_PAD_CONF("SW03: FST_SPI_D3", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 3, NA, 0x4418, SOUTHWEST),
+	GPIO_PAD_CONF("SW30: MF_HDA_CLK", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 16, NA, 0x4c00, SOUTHWEST),
+	GPIO_PAD_CONF("SW37: MF_HDA_DOCKENB", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 23, NA, 0x4c38, SOUTHWEST),
+	GPIO_PAD_CONF("SW34: MF_HDA_DOCKRSTB", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 20, NA, 0x4c20, SOUTHWEST),
+	GPIO_PAD_CONF("SW31: MF_HDA_RSTB", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 17, NA, 0x4c08, SOUTHWEST),
+	GPIO_PAD_CONF("SW32: MF_HDA_SDI0", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 18, NA, 0x4c10, SOUTHWEST),
+	GPIO_PAD_CONF("SW36: MF_HDA_SDI1", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 22, NA, 0x4c30, SOUTHWEST),
+	GPIO_PAD_CONF("SW33: MF_HDA_SDO", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 19, NA, 0x4c18, SOUTHWEST),
+	GPIO_PAD_CONF("SW35: MF_HDA_SYNC", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 21, NA, 0x4c28, SOUTHWEST),
+	GPIO_PAD_CONF("SW18: UART1_CTS_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 11, NA, 0x4818, SOUTHWEST),
+	GPIO_PAD_CONF("SW15: UART1_RTS_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 8, NA, 0x4800, SOUTHWEST),
+	GPIO_PAD_CONF("SW16: UART1_RXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 9, NA, 0x4808, SOUTHWEST),
+	GPIO_PAD_CONF("SW20: UART1_TXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 13, NA, 0x4828, SOUTHWEST),
+	GPIO_PAD_CONF("SW22: UART2_CTS_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 15, NA, 0x4838, SOUTHWEST),
+	GPIO_PAD_CONF("SW19: UART2_RTS_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 12, NA, 0x4820, SOUTHWEST),
+	GPIO_PAD_CONF("SW17: UART2_RXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 10, NA, 0x4810, SOUTHWEST),
+	GPIO_PAD_CONF("SW21: UART2_TXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 14, NA, 0x4830, SOUTHWEST),
+	GPIO_PAD_CONF("SW50: I2C4_SCL", NATIVE, M3, NA, NA, NA,
+		      NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 29, NA, 0x5028, SOUTHWEST),
+	GPIO_PAD_CONF("SW46: I2C4_SDA", NATIVE, M3, NA, NA, NA,
+		      NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 25, NA, 0x5008, SOUTHWEST),
+	GPIO_PAD_CONF("SW49: I2C_NFC_SDA", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 28, NA, 0x5020, SOUTHWEST),
+	GPIO_PAD_CONF("SW52: I2C_NFC_SCL", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 31, NA, 0x5038, SOUTHWEST),
+	GPIO_PAD_CONF("SW77: GP_SSP_2_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 50, NA, 0x5c10, SOUTHWEST),
+	GPIO_PAD_CONF("SW81: GP_SSP_2_FS", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 54, NA, 0x5c30, SOUTHWEST),
+	GPIO_PAD_CONF("SW79: GP_SSP_2_RXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 52, NA, 0x5c20, SOUTHWEST),
+	GPIO_PAD_CONF("SW82: GP_SSP_2_TXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 55, NA, 0x5C38, SOUTHWEST),
+	GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 48, NA, 0x5c00, SOUTHWEST),
+	GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 49, NA, 0x5c08, SOUTHWEST),
+	GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 51, NA, 0x5c18, SOUTHWEST),
+	GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 53, NA, 0x5c28, SOUTHWEST),
+	GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 40, NA, 0x5800, SOUTHWEST),
+	GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 41, NA, 0x5808, SOUTHWEST),
+	GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,
+		      NA, 43, NA, 0x5818, SOUTHWEST),
+	GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 45, NA, 0x5828, SOUTHWEST),
+	GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,
+		      NA, 42, NA, 0x5810, SOUTHWEST),
+	GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA,
+		      NA, NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 44, NA, 0x5820, SOUTHWEST),
+	GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 46, NA, 0x5830, SOUTHWEST),
+	GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 47, NA, 0x5838, SOUTHWEST),
+	GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NA,
+		      NA, 48, NA, 0x5c00, SOUTHWEST),
+	GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NA,
+		      NA, 49, NA, 0x5c08, SOUTHWEST),
+	GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NA,
+		      NA, 51, NA, 0x5c18, SOUTHWEST),
+	GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NA,
+		      NA, 53, NA, 0x5c28, SOUTHWEST),
+	GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA,
+		      NA, 40, NA, 0x5800, SOUTHWEST),
+	GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA,
+		      NA, 41, NA, 0x5808, SOUTHWEST),
+	GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, ENABLE, NA, NA, NA, NA,
+		      NA, 43, NA, 0x5818, SOUTHWEST),
+	GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NA,
+		      NA, 45, NA, 0x5828, SOUTHWEST),
+	GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, ENABLE, NA, NA, NA, NA,
+		      NA, 42, NA, 0x5810, SOUTHWEST),
+	GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA,
+		      NA, NA, NA, P_20K_H, NA, NA, NA, NA, NA,
+		      NA, 44, NA, 0x5820, SOUTHWEST),
+	GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NA,
+		      NA, 46, NA, 0x5830, SOUTHWEST),
+	GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NA,
+		      NA, 47, NA, 0x5838, SOUTHWEST),
+
+	/* end of the table */
+	GPIO_PAD_CONF("GPIO PAD TABLE END", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 0, NA, 0, TERMINATOR),
+};
+
+void update_fsp_gpio_configs(const struct gpio_family **family,
+			     const struct gpio_pad **pad)
+{
+	*family = gpio_family;
+	*pad = gpio_pad;
+}
diff --git a/board/intel/cherryhill/start.S b/board/intel/cherryhill/start.S
new file mode 100644
index 0000000..11af9de
--- /dev/null
+++ b/board/intel/cherryhill/start.S
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+	jmp	early_board_init_ret
diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig
new file mode 100644
index 0000000..a2017ac
--- /dev/null
+++ b/configs/cherryhill_defconfig
@@ -0,0 +1,36 @@
+CONFIG_X86=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_DEFAULT_DEVICE_TREE="cherryhill"
+CONFIG_TARGET_CHERRYHILL=y
+CONFIG_DEBUG_UART=y
+CONFIG_SMP=y
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_RTL8169=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
diff --git a/doc/README.x86 b/doc/README.x86
index c542a69..c96a22c 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -26,6 +26,7 @@ In this case, known as bare mode, from the fact that it runs on the
 are supported:
 
    - Bayley Bay CRB
+   - Cherry Hill CRB
    - Congatec QEVAL 2.0 & conga-QA3/E3845
    - Cougar Canyon 2 CRB
    - Crown Bay CRB
@@ -332,6 +333,35 @@ the default value 0xfffc0000.
 
 ---
 
+Intel Cherry Hill specific instructions for bare mode:
+
+This uses Intel FSP for Braswell platform. Download it from Intel FSP website,
+put the .fd file to the board directory and rename it to fsp.bin.
+
+Extract descriptor.bin and me.bin from the original BIOS on the board using
+ifdtool and put them to the board directory as well.
+
+Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS
+image for the integrated graphics device. Instead a new binary called Video
+BIOS Table (VBT) is shipped. Put it to the board directory and rename it to
+vbt.bin if you want graphics support in U-Boot.
+
+Now you can build U-Boot and obtain u-boot.rom
+
+$ make cherryhill_defconfig
+$ make all
+
+An important note for programming u-boot.rom to the on-board SPI flash is that
+you need make sure the SPI flash's 'quad enable' bit in its status register
+matches the settings in the descriptor.bin, otherwise the board won't boot.
+
+For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the
+status register by DediProg in: Config > Modify Status Register > Write Status
+Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it
+persists in SPI flash part regardless of the u-boot.rom image burned.
+
+---
+
 Intel Galileo instructions for bare mode:
 
 Only one binary blob is needed for Remote Management Unit (RMU) within Intel
diff --git a/include/configs/cherryhill.h b/include/configs/cherryhill.h
new file mode 100644
index 0000000..14da9ca
--- /dev/null
+++ b/include/configs/cherryhill.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(2 << 20)
+
+#define CONFIG_STD_DEVICES_SETTINGS	"stdin=usbkbd,serial\0" \
+					"stdout=vidconsole,serial\0" \
+					"stderr=vidconsole,serial\0"
+
+/* Environment configuration */
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#define CONFIG_ENV_OFFSET		0x005f0000
+
+#endif	/* __CONFIG_H */
-- 
2.9.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 07/13] x86: dm: video: Add a framebuffer driver that utilizes VBT
  2017-08-16  5:41 ` [U-Boot] [PATCH 07/13] x86: dm: video: Add a framebuffer driver that utilizes VBT Bin Meng
@ 2017-08-26  3:36   ` Simon Glass
  2017-09-02 16:11     ` Bin Meng
  0 siblings, 1 reply; 47+ messages in thread
From: Simon Glass @ 2017-08-26  3:36 UTC (permalink / raw
  To: u-boot

On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
> When a VBT is given to an FSP that supports graphics initialization,
> the FSP will produce a graphics info HOB that contains all necessary
> information for the linear frame buffer of the integrated graphics
> device. This adds a DM video driver for it.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/Kconfig                |   8 +++
>  arch/x86/lib/fsp/Makefile       |   1 +
>  arch/x86/lib/fsp/fsp_graphics.c | 124 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 133 insertions(+)
>  create mode 100644 arch/x86/lib/fsp/fsp_graphics.c

Reviewed-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 01/13] x86: tsc: Add Airmont reference clock values
  2017-08-16  5:41 ` [U-Boot] [PATCH 01/13] x86: tsc: Add Airmont reference clock values Bin Meng
@ 2017-08-26 13:38   ` Simon Glass
  2017-09-02 16:11     ` Bin Meng
  0 siblings, 1 reply; 47+ messages in thread
From: Simon Glass @ 2017-08-26 13:38 UTC (permalink / raw
  To: u-boot

On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
> Per the Intel 64 and IA-32 Architecture Software Developer's Manual,
> add the reference clock for Intel Atom Processors based on the Airmont
> Microarchitecture (Braswell).
>
> This keeps in sync with Linux kernel commit:
>   6fcb41c: x86/tsc_msr: Add Airmont reference clock values
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  drivers/timer/tsc_timer.c | 17 ++++++++++-------
>  1 file changed, 10 insertions(+), 7 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 02/13] x86: fsp: Update struct common_buf for FSP spec 1.1
  2017-08-16  5:41 ` [U-Boot] [PATCH 02/13] x86: fsp: Update struct common_buf for FSP spec 1.1 Bin Meng
@ 2017-08-26 13:38   ` Simon Glass
  2017-09-02 16:11     ` Bin Meng
  0 siblings, 1 reply; 47+ messages in thread
From: Simon Glass @ 2017-08-26 13:38 UTC (permalink / raw
  To: u-boot

On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
> FSP spec 1.1 adds one more member to the struct common_buf to
> determine the memory size that can be reserved by FSP below "top
> of low usable memory" for bootloader usage. This new member uses
> the reserved space so that it is still compatible with previous
> FSP spec 1.0.
>
> A new HOB (FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID) is also
> published when common_buf.tolum_size is valid and non zero.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/include/asm/fsp/fsp_api.h | 3 ++-
>  arch/x86/include/asm/fsp/fsp_hob.h | 8 ++++++++
>  2 files changed, 10 insertions(+), 1 deletion(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 03/13] x86: fsp: Add FSP_GRAPHICS_INFO_HOB
  2017-08-16  5:41 ` [U-Boot] [PATCH 03/13] x86: fsp: Add FSP_GRAPHICS_INFO_HOB Bin Meng
@ 2017-08-26 13:38   ` Simon Glass
  2017-09-02 16:11     ` Bin Meng
  0 siblings, 1 reply; 47+ messages in thread
From: Simon Glass @ 2017-08-26 13:38 UTC (permalink / raw
  To: u-boot

On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
> This adds a new HOB type for graphics information introduced in FSP
> spec 1.1. When graphics capability is included in FSP and enabled,
> FSP produces an FSP_GRAPHICS_INFO_HOB as described in the EFI PI
> specification which provides information about the graphics mode and
> framebuffer.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/include/asm/fsp/fsp_hob.h     | 26 ++++++++++++++++++++++++++
>  arch/x86/include/asm/fsp/fsp_support.h | 12 ++++++++++++
>  arch/x86/lib/fsp/fsp_support.c         |  7 +++++++
>  3 files changed, 45 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 04/13] x86: Add Video BIOS Table (VBT) related Kconfig options
  2017-08-16  5:41 ` [U-Boot] [PATCH 04/13] x86: Add Video BIOS Table (VBT) related Kconfig options Bin Meng
@ 2017-08-26 13:38   ` Simon Glass
  2017-09-02 16:11     ` Bin Meng
  0 siblings, 1 reply; 47+ messages in thread
From: Simon Glass @ 2017-08-26 13:38 UTC (permalink / raw
  To: u-boot

On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
> This adds Kconfig options for Video BIOS Table which is normally
> required if you are using an Intel FSP firmware that is complaint
> with spec 1.1 or later to initialize the integrated graphics device.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/Kconfig | 34 ++++++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 05/13] tools: binman: Add a new entry type for Intel VBT
  2017-08-16  5:41 ` [U-Boot] [PATCH 05/13] tools: binman: Add a new entry type for Intel VBT Bin Meng
@ 2017-08-26 13:38   ` Simon Glass
  2017-09-02 16:11     ` Bin Meng
  0 siblings, 1 reply; 47+ messages in thread
From: Simon Glass @ 2017-08-26 13:38 UTC (permalink / raw
  To: u-boot

On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
> This adds a new entry type for Intel Video BIOS Table.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  tools/binman/etype/intel_vbt.py    | 14 ++++++++++++++
>  tools/binman/func_test.py          |  9 ++++++++-
>  tools/binman/test/46_intel-vbt.dts | 14 ++++++++++++++
>  3 files changed, 36 insertions(+), 1 deletion(-)
>  create mode 100644 tools/binman/etype/intel_vbt.py
>  create mode 100644 tools/binman/test/46_intel-vbt.dts

Reviewed-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 06/13] x86: dts: Include Intel Video BIOS Table in the ROM image
  2017-08-16  5:41 ` [U-Boot] [PATCH 06/13] x86: dts: Include Intel Video BIOS Table in the ROM image Bin Meng
@ 2017-08-26 13:39   ` Simon Glass
  2017-09-02 16:11     ` Bin Meng
  0 siblings, 1 reply; 47+ messages in thread
From: Simon Glass @ 2017-08-26 13:39 UTC (permalink / raw
  To: u-boot

On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
> Now that binman is able to recognize the Video BIOS Table entry,
> add such one in the u-boot.dtsi.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/dts/u-boot.dtsi | 6 ++++++
>  1 file changed, 6 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 08/13] x86: fsp: Update fsp command to show spec 1.1 header
  2017-08-16  5:41 ` [U-Boot] [PATCH 08/13] x86: fsp: Update fsp command to show spec 1.1 header Bin Meng
@ 2017-08-26 13:39   ` Simon Glass
  2017-09-02 16:11     ` Bin Meng
  0 siblings, 1 reply; 47+ messages in thread
From: Simon Glass @ 2017-08-26 13:39 UTC (permalink / raw
  To: u-boot

On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
> FSP spec 1.1 adds 3 new APIs and their offsets are in the header.
> Update the 'fsp hdr' command to show these new entries.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/include/asm/fsp/fsp_infoheader.h |  9 ++++++++-
>  arch/x86/lib/fsp/cmd_fsp.c                | 24 ++++++++++++++++++++++--
>  2 files changed, 30 insertions(+), 3 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 09/13] x86: Add Intel Braswell SoC support
  2017-08-16  5:41 ` [U-Boot] [PATCH 09/13] x86: Add Intel Braswell SoC support Bin Meng
@ 2017-08-26 13:39   ` Simon Glass
  2017-08-26 13:55     ` Bin Meng
  0 siblings, 1 reply; 47+ messages in thread
From: Simon Glass @ 2017-08-26 13:39 UTC (permalink / raw
  To: u-boot

On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
> This adds initial Intel Braswell SoC support. It uses Intel FSP
> to initialize the chipset.
>
> Similar to its predecessor BayTrail, there are some work to do to
> enable the legacy UART integrated in the Braswell SoC.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/Kconfig                           |   1 +
>  arch/x86/cpu/Makefile                      |   1 +
>  arch/x86/cpu/braswell/Kconfig              |  38 +++++++
>  arch/x86/cpu/braswell/Makefile             |   7 ++
>  arch/x86/cpu/braswell/braswell.c           |  36 ++++++
>  arch/x86/cpu/braswell/cpu.c                | 170 +++++++++++++++++++++++++++++
>  arch/x86/cpu/braswell/early_uart.c         |  86 +++++++++++++++
>  arch/x86/include/asm/arch-braswell/iomap.h |  50 +++++++++
>  8 files changed, 389 insertions(+)
>  create mode 100644 arch/x86/cpu/braswell/Kconfig
>  create mode 100644 arch/x86/cpu/braswell/Makefile
>  create mode 100644 arch/x86/cpu/braswell/braswell.c
>  create mode 100644 arch/x86/cpu/braswell/cpu.c
>  create mode 100644 arch/x86/cpu/braswell/early_uart.c
>  create mode 100644 arch/x86/include/asm/arch-braswell/iomap.h

Reviewed-by: Simon Glass <sjg@chromium.org>

A few nits / suggestions below.

>
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index f72d307..9620764 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -108,6 +108,7 @@ source "board/intel/Kconfig"
>
>  # platform-specific options below
>  source "arch/x86/cpu/baytrail/Kconfig"
> +source "arch/x86/cpu/braswell/Kconfig"
>  source "arch/x86/cpu/broadwell/Kconfig"
>  source "arch/x86/cpu/coreboot/Kconfig"
>  source "arch/x86/cpu/ivybridge/Kconfig"
> diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
> index 999429e..94cdff1 100644
> --- a/arch/x86/cpu/Makefile
> +++ b/arch/x86/cpu/Makefile
> @@ -27,6 +27,7 @@ endif
>
>  obj-y += intel_common/
>  obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
> +obj-$(CONFIG_INTEL_BRASWELL) += braswell/
>  obj-$(CONFIG_INTEL_BROADWELL) += broadwell/
>  obj-$(CONFIG_SYS_COREBOOT) += coreboot/
>  obj-$(CONFIG_EFI_APP) += efi/
> diff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig
> new file mode 100644
> index 0000000..c993889
> --- /dev/null
> +++ b/arch/x86/cpu/braswell/Kconfig
> @@ -0,0 +1,38 @@
> +#
> +# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
> +#
> +# SPDX-License-Identifier:     GPL-2.0+
> +#
> +
> +config INTEL_BRASWELL
> +       bool
> +       select HAVE_FSP
> +       select ARCH_MISC_INIT
> +       imply HAVE_INTEL_ME
> +       imply HAVE_VBT
> +       imply ENABLE_MRC_CACHE
> +       imply ENV_IS_IN_SPI_FLASH
> +       imply AHCI_PCI
> +       imply ICH_SPI
> +       imply MMC
> +       imply MMC_PCI
> +       imply MMC_SDHCI
> +       imply MMC_SDHCI_SDMA
> +       imply SCSI
> +       imply SPI_FLASH
> +       imply SYS_NS16550
> +       imply USB
> +       imply USB_XHCI_HCD
> +       imply VIDEO_FSP
> +
> +if INTEL_BRASWELL
> +
> +config FSP_ADDR
> +       hex
> +       default 0xfff20000
> +
> +config FSP_LOCKDOWN_SPI
> +       bool
> +       default y
> +
> +endif
> diff --git a/arch/x86/cpu/braswell/Makefile b/arch/x86/cpu/braswell/Makefile
> new file mode 100644
> index 0000000..19bcee6
> --- /dev/null
> +++ b/arch/x86/cpu/braswell/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
> +#
> +# SPDX-License-Identifier:     GPL-2.0+
> +#
> +
> +obj-y += braswell.o cpu.o early_uart.o
> diff --git a/arch/x86/cpu/braswell/braswell.c b/arch/x86/cpu/braswell/braswell.c
> new file mode 100644
> index 0000000..37099aa
> --- /dev/null
> +++ b/arch/x86/cpu/braswell/braswell.c
> @@ -0,0 +1,36 @@
> +/*
> + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/mrccache.h>
> +#include <asm/post.h>
> +
> +int arch_cpu_init(void)
> +{
> +       post_code(POST_CPU_INIT);
> +
> +       return x86_cpu_init_f();
> +}
> +
> +int arch_misc_init(void)
> +{
> +#ifdef CONFIG_ENABLE_MRC_CACHE
> +       /*
> +        * We intend not to check any return value here, as even MRC cache
> +        * is not saved successfully, it is not a severe error that will
> +        * prevent system from continuing to boot.
> +        */
> +       mrccache_save();
> +#endif
> +
> +       return 0;
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> +       /* cold reset */
> +       x86_full_reset();
> +}
> diff --git a/arch/x86/cpu/braswell/cpu.c b/arch/x86/cpu/braswell/cpu.c
> new file mode 100644
> index 0000000..6ff9036
> --- /dev/null
> +++ b/arch/x86/cpu/braswell/cpu.c
> @@ -0,0 +1,170 @@
> +/*
> + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + *
> + * Derived from arch/x86/cpu/baytrail/cpu.c
> + */
> +
> +#include <common.h>
> +#include <cpu.h>
> +#include <dm.h>
> +#include <asm/cpu.h>
> +#include <asm/cpu_x86.h>
> +#include <asm/io.h>
> +#include <asm/lapic.h>
> +#include <asm/msr.h>
> +#include <asm/turbo.h>
> +
> +static const unsigned int braswell_bus_freq_table[] = {
> +       83333333,
> +       100000000,
> +       133333333,
> +       116666666,
> +       80000000,
> +       93333333,
> +       90000000,
> +       88900000,
> +       87500000
> +};
> +
> +static unsigned int braswell_bus_freq(void)
> +{
> +       msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
> +
> +       if ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table)))
> +               return braswell_bus_freq_table[clk_info.lo & 0xf];
> +
> +       return 0;
> +}
> +
> +static unsigned long braswell_tsc_freq(void)
> +{
> +       msr_t platform_info;
> +       ulong bclk = braswell_bus_freq();
> +
> +       if (!bclk)
> +               return 0;
> +
> +       platform_info = msr_read(MSR_PLATFORM_INFO);
> +
> +       return bclk * ((platform_info.lo >> 8) & 0xff);
> +}
> +
> +static int braswell_get_info(struct udevice *dev, struct cpu_info *info)
> +{
> +       info->cpu_freq = braswell_tsc_freq();
> +       info->features = (1 << CPU_FEAT_L1_CACHE) | (1 << CPU_FEAT_MMU);
> +
> +       return 0;
> +}
> +
> +static int braswell_get_count(struct udevice *dev)
> +{
> +       int ecx = 0;
> +
> +       /*
> +        * Use the algorithm described in Intel 64 and IA-32 Architectures
> +        * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
> +        * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
> +        * of CPUID Extended Topology Leaf.
> +        */
> +       while (1) {
> +               struct cpuid_result leaf_b;
> +
> +               leaf_b = cpuid_ext(0xb, ecx);
> +
> +               /*
> +                * Braswell doesn't have hyperthreading so just determine the
> +                * number of cores by from level type (ecx[15:8] == * 2)
> +                */
> +               if ((leaf_b.ecx & 0xff00) == 0x0200)
> +                       return leaf_b.ebx & 0xffff;
> +
> +               ecx++;
> +       }
> +
> +       return 0;
> +}
> +
> +static void braswell_set_max_freq(void)
> +{
> +       msr_t perf_ctl;
> +       msr_t msr;
> +
> +       /* Enable speed step */
> +       msr = msr_read(MSR_IA32_MISC_ENABLES);
> +       msr.lo |= (1 << 16);
> +       msr_write(MSR_IA32_MISC_ENABLES, msr);
> +
> +       /* Enable Burst Mode */
> +       msr = msr_read(MSR_IA32_MISC_ENABLES);
> +       msr.hi = 0;
> +       msr_write(MSR_IA32_MISC_ENABLES, msr);
> +
> +       /*
> +        * Set guaranteed ratio [21:16] from IACORE_TURBO_RATIOS to
> +        * bits [15:8] of the PERF_CTL
> +        */
> +       msr = msr_read(MSR_IACORE_TURBO_RATIOS);
> +       perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
> +
> +       /*
> +        * Set guaranteed vid [22:16] from IACORE_TURBO_VIDS to
> +        * bits [7:0] of the PERF_CTL
> +        */
> +       msr = msr_read(MSR_IACORE_TURBO_VIDS);
> +       perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
> +
> +       perf_ctl.hi = 0;
> +       msr_write(MSR_IA32_PERF_CTL, perf_ctl);
> +}
> +
> +static int braswell_probe(struct udevice *dev)
> +{
> +       debug("Init Braswell core\n");
> +
> +       /*
> +        * On Braswell the turbo disable bit is actually scoped at the
> +        * building-block level, not package. For non-BSP cores that are
> +        * within a building block, enable turbo. The cores within the BSP's
> +        * building block will just see it already enabled and move on.
> +        */
> +       if (lapicid())
> +               turbo_enable();
> +
> +       /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
> +       msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f080f, 0xe0008),
> +       msr_clrsetbits_64(MSR_POWER_MISC,
> +                         ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK, 0);
> +
> +       /* Disable C1E */
> +       msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);
> +       msr_setbits_64(MSR_POWER_MISC, 0x44);
> +
> +       /* Set this core to max frequency ratio */
> +       braswell_set_max_freq();
> +
> +       return 0;
> +}
> +
> +static const struct udevice_id braswell_ids[] = {
> +       { .compatible = "intel,braswell-cpu" },
> +       { }
> +};
> +
> +static const struct cpu_ops braswell_ops = {
> +       .get_desc       = cpu_x86_get_desc,
> +       .get_info       = braswell_get_info,
> +       .get_count      = braswell_get_count,
> +       .get_vendor     = cpu_x86_get_vendor,
> +};
> +
> +U_BOOT_DRIVER(cpu_x86_braswell_drv) = {
> +       .name           = "cpu_x86_braswell",
> +       .id             = UCLASS_CPU,
> +       .of_match       = braswell_ids,
> +       .bind           = cpu_x86_bind,
> +       .probe          = braswell_probe,
> +       .ops            = &braswell_ops,
> +};
> diff --git a/arch/x86/cpu/braswell/early_uart.c b/arch/x86/cpu/braswell/early_uart.c
> new file mode 100644
> index 0000000..0300e13
> --- /dev/null
> +++ b/arch/x86/cpu/braswell/early_uart.c
> @@ -0,0 +1,86 @@
> +/*
> + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +
> +#define PCI_DEV_CONFIG(segbus, dev, fn) ( \
> +               (((segbus) & 0xfff) << 20) | \
> +               (((dev) & 0x1f) << 15) | \
> +               (((fn)  & 0x07) << 12))

This seems to be shared by baytrail? Do you think it should go in a header file?

> +
> +/* Platform Controller Unit */
> +#define LPC_DEV                        0x1f
> +#define LPC_FUNC               0
> +
> +/* Enable UART */
> +#define UART_CONT              0x80
> +
> +/* UART PAD definitions */
> +#define UART_RXD_COMMUITY      1
> +#define UART_TXD_COMMUITY      1
> +#define UART_RXD_FAMILY                4
> +#define UART_TXD_FAMILY                4
> +#define UART_RXD_PAD           2
> +#define UART_TXD_PAD           7
> +#define UART_RXD_FUNC          3
> +#define UART_TXD_FUNC          3
> +
> +/* IO Memory */
> +#define IO_BASE_ADDRESS                0xfed80000
> +
> +static inline uint32_t gpio_pconf0(int community, int family, int pad)
> +{
> +       return IO_BASE_ADDRESS + community * 0x8000 + 0x4400 +
> +               family * 0x400 + pad * 8;
> +}
> +
> +static void gpio_select_func(int community, int family, int pad, int func)
> +{
> +       uint32_t reg;
> +       uint32_t pconf0_addr = gpio_pconf0(community, family, pad);
> +
> +       reg = readl(pconf0_addr);
> +       reg &= ~(0xf << 16);
> +       reg |= (func << 16);
> +       writel(reg, pconf0_addr);

Can we use setclrbits_le32()?

> +}
> +
> +static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
> +{
> +       unsigned long addr;
> +
> +       addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
> +       writel(value, addr);
> +}
> +

Regards,
Simon

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 10/13] x86: braswell: Add microcode for B0/C0/D0 stepping SoC
  2017-08-16  5:41 ` [U-Boot] [PATCH 10/13] x86: braswell: Add microcode for B0/C0/D0 stepping SoC Bin Meng
@ 2017-08-26 13:39   ` Simon Glass
  2017-09-16  4:32     ` Bin Meng
  0 siblings, 1 reply; 47+ messages in thread
From: Simon Glass @ 2017-08-26 13:39 UTC (permalink / raw
  To: u-boot

On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
> This adds microcode device tree fragment for Braswell B0 (406C2),
> C0 (406C3) and D0 (406C4) stepping SoC.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/dts/microcode/m01406c2220.dtsi | 4308 +++++++++++++++++++++++++++++++
>  arch/x86/dts/microcode/m01406c3363.dtsi | 4308 +++++++++++++++++++++++++++++++
>  arch/x86/dts/microcode/m01406c440a.dtsi | 4308 +++++++++++++++++++++++++++++++
>  3 files changed, 12924 insertions(+)
>  create mode 100644 arch/x86/dts/microcode/m01406c2220.dtsi
>  create mode 100644 arch/x86/dts/microcode/m01406c3363.dtsi
>  create mode 100644 arch/x86/dts/microcode/m01406c440a.dtsi

Reviewed-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 11/13] x86: braswell: Add FSP configuration
  2017-08-16  5:42 ` [U-Boot] [PATCH 11/13] x86: braswell: Add FSP configuration Bin Meng
@ 2017-08-26 13:39   ` Simon Glass
  2017-08-26 13:56     ` Bin Meng
  2017-09-16  4:32     ` Bin Meng
  0 siblings, 2 replies; 47+ messages in thread
From: Simon Glass @ 2017-08-26 13:39 UTC (permalink / raw
  To: u-boot

On 15 August 2017 at 23:42, Bin Meng <bmeng.cn@gmail.com> wrote:
> Add FSP related configuration for Braswell.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/braswell/Makefile                     |   2 +-
>  arch/x86/cpu/braswell/fsp_configs.c                | 158 ++++++++++++++
>  .../include/asm/arch-braswell/fsp/fsp_configs.h    |  89 ++++++++
>  arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h   | 172 +++++++++++++++
>  arch/x86/include/asm/arch-braswell/gpio.h          | 234 +++++++++++++++++++++
>  5 files changed, 654 insertions(+), 1 deletion(-)
>  create mode 100644 arch/x86/cpu/braswell/fsp_configs.c
>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
>  create mode 100644 arch/x86/include/asm/arch-braswell/gpio.h
>

Reviewed-by: Simon Glass <sjg@chromium.org>

Can this use drivers instead of manual device-tree access?

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 12/13] x86: braswell: Disable PUNIT power configuration for B0 stepping
  2017-08-16  5:42 ` [U-Boot] [PATCH 12/13] x86: braswell: Disable PUNIT power configuration for B0 stepping Bin Meng
@ 2017-08-26 13:39   ` Simon Glass
  2017-09-16  4:32     ` Bin Meng
  0 siblings, 1 reply; 47+ messages in thread
From: Simon Glass @ 2017-08-26 13:39 UTC (permalink / raw
  To: u-boot

On 15 August 2017 at 23:42, Bin Meng <bmeng.cn@gmail.com> wrote:
> FSP's built-in UPD configuration enables PUNIT power configuration,
> but on B0 stepping, this causes CPU hangs in fsp_init(). Disable it.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/braswell/fsp_configs.c | 6 ++++++
>  1 file changed, 6 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 13/13] x86: Support Intel Cherry Hill board
  2017-08-16  5:42 ` [U-Boot] [PATCH 13/13] x86: Support Intel Cherry Hill board Bin Meng
@ 2017-08-26 13:39   ` Simon Glass
  2017-09-16  4:32     ` Bin Meng
  0 siblings, 1 reply; 47+ messages in thread
From: Simon Glass @ 2017-08-26 13:39 UTC (permalink / raw
  To: u-boot

On 15 August 2017 at 23:42, Bin Meng <bmeng.cn@gmail.com> wrote:
> This adds support to Intel Cherry Hill board, a board based on
> Intel Braswell SoC. The following devices are validated:
>
> - serial port as the serial console
> - on-board Realtek 8169 ethernet controller
> - SATA AHCI controller
> - EMMC/SDHC controller
> - USB 3.0 xHCI controller
> - PCIe x1 slot with a graphics card
> - ICH SPI controller with an 8MB Macronix SPI flash
> - Integrated graphics device as the video console
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
>  arch/x86/dts/Makefile               |   1 +
>  arch/x86/dts/cherryhill.dts         | 215 +++++++++++++
>  board/intel/Kconfig                 |  10 +
>  board/intel/cherryhill/Kconfig      |  25 ++
>  board/intel/cherryhill/MAINTAINERS  |   6 +
>  board/intel/cherryhill/Makefile     |   7 +
>  board/intel/cherryhill/cherryhill.c | 596 ++++++++++++++++++++++++++++++++++++
>  board/intel/cherryhill/start.S      |   9 +
>  configs/cherryhill_defconfig        |  36 +++
>  doc/README.x86                      |  30 ++
>  include/configs/cherryhill.h        |  22 ++
>  11 files changed, 957 insertions(+)
>  create mode 100644 arch/x86/dts/cherryhill.dts
>  create mode 100644 board/intel/cherryhill/Kconfig
>  create mode 100644 board/intel/cherryhill/MAINTAINERS
>  create mode 100644 board/intel/cherryhill/Makefile
>  create mode 100644 board/intel/cherryhill/cherryhill.c
>  create mode 100644 board/intel/cherryhill/start.S
>  create mode 100644 configs/cherryhill_defconfig
>  create mode 100644 include/configs/cherryhill.h

Reviewed-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 09/13] x86: Add Intel Braswell SoC support
  2017-08-26 13:39   ` Simon Glass
@ 2017-08-26 13:55     ` Bin Meng
  2017-09-16  4:32       ` Bin Meng
  0 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-26 13:55 UTC (permalink / raw
  To: u-boot

Hi Simon,

On Sat, Aug 26, 2017 at 9:39 PM, Simon Glass <sjg@chromium.org> wrote:
> On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
>> This adds initial Intel Braswell SoC support. It uses Intel FSP
>> to initialize the chipset.
>>
>> Similar to its predecessor BayTrail, there are some work to do to
>> enable the legacy UART integrated in the Braswell SoC.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/Kconfig                           |   1 +
>>  arch/x86/cpu/Makefile                      |   1 +
>>  arch/x86/cpu/braswell/Kconfig              |  38 +++++++
>>  arch/x86/cpu/braswell/Makefile             |   7 ++
>>  arch/x86/cpu/braswell/braswell.c           |  36 ++++++
>>  arch/x86/cpu/braswell/cpu.c                | 170 +++++++++++++++++++++++++++++
>>  arch/x86/cpu/braswell/early_uart.c         |  86 +++++++++++++++
>>  arch/x86/include/asm/arch-braswell/iomap.h |  50 +++++++++
>>  8 files changed, 389 insertions(+)
>>  create mode 100644 arch/x86/cpu/braswell/Kconfig
>>  create mode 100644 arch/x86/cpu/braswell/Makefile
>>  create mode 100644 arch/x86/cpu/braswell/braswell.c
>>  create mode 100644 arch/x86/cpu/braswell/cpu.c
>>  create mode 100644 arch/x86/cpu/braswell/early_uart.c
>>  create mode 100644 arch/x86/include/asm/arch-braswell/iomap.h
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> A few nits / suggestions below.
>
>>
>> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
>> index f72d307..9620764 100644
>> --- a/arch/x86/Kconfig
>> +++ b/arch/x86/Kconfig
>> @@ -108,6 +108,7 @@ source "board/intel/Kconfig"
>>
>>  # platform-specific options below
>>  source "arch/x86/cpu/baytrail/Kconfig"
>> +source "arch/x86/cpu/braswell/Kconfig"
>>  source "arch/x86/cpu/broadwell/Kconfig"
>>  source "arch/x86/cpu/coreboot/Kconfig"
>>  source "arch/x86/cpu/ivybridge/Kconfig"
>> diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
>> index 999429e..94cdff1 100644
>> --- a/arch/x86/cpu/Makefile
>> +++ b/arch/x86/cpu/Makefile
>> @@ -27,6 +27,7 @@ endif
>>
>>  obj-y += intel_common/
>>  obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
>> +obj-$(CONFIG_INTEL_BRASWELL) += braswell/
>>  obj-$(CONFIG_INTEL_BROADWELL) += broadwell/
>>  obj-$(CONFIG_SYS_COREBOOT) += coreboot/
>>  obj-$(CONFIG_EFI_APP) += efi/
>> diff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig
>> new file mode 100644
>> index 0000000..c993889
>> --- /dev/null
>> +++ b/arch/x86/cpu/braswell/Kconfig
>> @@ -0,0 +1,38 @@
>> +#
>> +# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
>> +#
>> +# SPDX-License-Identifier:     GPL-2.0+
>> +#
>> +
>> +config INTEL_BRASWELL
>> +       bool
>> +       select HAVE_FSP
>> +       select ARCH_MISC_INIT
>> +       imply HAVE_INTEL_ME
>> +       imply HAVE_VBT
>> +       imply ENABLE_MRC_CACHE
>> +       imply ENV_IS_IN_SPI_FLASH
>> +       imply AHCI_PCI
>> +       imply ICH_SPI
>> +       imply MMC
>> +       imply MMC_PCI
>> +       imply MMC_SDHCI
>> +       imply MMC_SDHCI_SDMA
>> +       imply SCSI
>> +       imply SPI_FLASH
>> +       imply SYS_NS16550
>> +       imply USB
>> +       imply USB_XHCI_HCD
>> +       imply VIDEO_FSP
>> +
>> +if INTEL_BRASWELL
>> +
>> +config FSP_ADDR
>> +       hex
>> +       default 0xfff20000
>> +
>> +config FSP_LOCKDOWN_SPI
>> +       bool
>> +       default y
>> +
>> +endif
>> diff --git a/arch/x86/cpu/braswell/Makefile b/arch/x86/cpu/braswell/Makefile
>> new file mode 100644
>> index 0000000..19bcee6
>> --- /dev/null
>> +++ b/arch/x86/cpu/braswell/Makefile
>> @@ -0,0 +1,7 @@
>> +#
>> +# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
>> +#
>> +# SPDX-License-Identifier:     GPL-2.0+
>> +#
>> +
>> +obj-y += braswell.o cpu.o early_uart.o
>> diff --git a/arch/x86/cpu/braswell/braswell.c b/arch/x86/cpu/braswell/braswell.c
>> new file mode 100644
>> index 0000000..37099aa
>> --- /dev/null
>> +++ b/arch/x86/cpu/braswell/braswell.c
>> @@ -0,0 +1,36 @@
>> +/*
>> + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
>> + *
>> + * SPDX-License-Identifier:    GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/mrccache.h>
>> +#include <asm/post.h>
>> +
>> +int arch_cpu_init(void)
>> +{
>> +       post_code(POST_CPU_INIT);
>> +
>> +       return x86_cpu_init_f();
>> +}
>> +
>> +int arch_misc_init(void)
>> +{
>> +#ifdef CONFIG_ENABLE_MRC_CACHE
>> +       /*
>> +        * We intend not to check any return value here, as even MRC cache
>> +        * is not saved successfully, it is not a severe error that will
>> +        * prevent system from continuing to boot.
>> +        */
>> +       mrccache_save();
>> +#endif
>> +
>> +       return 0;
>> +}
>> +
>> +void reset_cpu(ulong addr)
>> +{
>> +       /* cold reset */
>> +       x86_full_reset();
>> +}
>> diff --git a/arch/x86/cpu/braswell/cpu.c b/arch/x86/cpu/braswell/cpu.c
>> new file mode 100644
>> index 0000000..6ff9036
>> --- /dev/null
>> +++ b/arch/x86/cpu/braswell/cpu.c
>> @@ -0,0 +1,170 @@
>> +/*
>> + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
>> + *
>> + * SPDX-License-Identifier:    GPL-2.0+
>> + *
>> + * Derived from arch/x86/cpu/baytrail/cpu.c
>> + */
>> +
>> +#include <common.h>
>> +#include <cpu.h>
>> +#include <dm.h>
>> +#include <asm/cpu.h>
>> +#include <asm/cpu_x86.h>
>> +#include <asm/io.h>
>> +#include <asm/lapic.h>
>> +#include <asm/msr.h>
>> +#include <asm/turbo.h>
>> +
>> +static const unsigned int braswell_bus_freq_table[] = {
>> +       83333333,
>> +       100000000,
>> +       133333333,
>> +       116666666,
>> +       80000000,
>> +       93333333,
>> +       90000000,
>> +       88900000,
>> +       87500000
>> +};
>> +
>> +static unsigned int braswell_bus_freq(void)
>> +{
>> +       msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
>> +
>> +       if ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table)))
>> +               return braswell_bus_freq_table[clk_info.lo & 0xf];
>> +
>> +       return 0;
>> +}
>> +
>> +static unsigned long braswell_tsc_freq(void)
>> +{
>> +       msr_t platform_info;
>> +       ulong bclk = braswell_bus_freq();
>> +
>> +       if (!bclk)
>> +               return 0;
>> +
>> +       platform_info = msr_read(MSR_PLATFORM_INFO);
>> +
>> +       return bclk * ((platform_info.lo >> 8) & 0xff);
>> +}
>> +
>> +static int braswell_get_info(struct udevice *dev, struct cpu_info *info)
>> +{
>> +       info->cpu_freq = braswell_tsc_freq();
>> +       info->features = (1 << CPU_FEAT_L1_CACHE) | (1 << CPU_FEAT_MMU);
>> +
>> +       return 0;
>> +}
>> +
>> +static int braswell_get_count(struct udevice *dev)
>> +{
>> +       int ecx = 0;
>> +
>> +       /*
>> +        * Use the algorithm described in Intel 64 and IA-32 Architectures
>> +        * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
>> +        * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
>> +        * of CPUID Extended Topology Leaf.
>> +        */
>> +       while (1) {
>> +               struct cpuid_result leaf_b;
>> +
>> +               leaf_b = cpuid_ext(0xb, ecx);
>> +
>> +               /*
>> +                * Braswell doesn't have hyperthreading so just determine the
>> +                * number of cores by from level type (ecx[15:8] == * 2)
>> +                */
>> +               if ((leaf_b.ecx & 0xff00) == 0x0200)
>> +                       return leaf_b.ebx & 0xffff;
>> +
>> +               ecx++;
>> +       }
>> +
>> +       return 0;
>> +}
>> +
>> +static void braswell_set_max_freq(void)
>> +{
>> +       msr_t perf_ctl;
>> +       msr_t msr;
>> +
>> +       /* Enable speed step */
>> +       msr = msr_read(MSR_IA32_MISC_ENABLES);
>> +       msr.lo |= (1 << 16);
>> +       msr_write(MSR_IA32_MISC_ENABLES, msr);
>> +
>> +       /* Enable Burst Mode */
>> +       msr = msr_read(MSR_IA32_MISC_ENABLES);
>> +       msr.hi = 0;
>> +       msr_write(MSR_IA32_MISC_ENABLES, msr);
>> +
>> +       /*
>> +        * Set guaranteed ratio [21:16] from IACORE_TURBO_RATIOS to
>> +        * bits [15:8] of the PERF_CTL
>> +        */
>> +       msr = msr_read(MSR_IACORE_TURBO_RATIOS);
>> +       perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
>> +
>> +       /*
>> +        * Set guaranteed vid [22:16] from IACORE_TURBO_VIDS to
>> +        * bits [7:0] of the PERF_CTL
>> +        */
>> +       msr = msr_read(MSR_IACORE_TURBO_VIDS);
>> +       perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
>> +
>> +       perf_ctl.hi = 0;
>> +       msr_write(MSR_IA32_PERF_CTL, perf_ctl);
>> +}
>> +
>> +static int braswell_probe(struct udevice *dev)
>> +{
>> +       debug("Init Braswell core\n");
>> +
>> +       /*
>> +        * On Braswell the turbo disable bit is actually scoped at the
>> +        * building-block level, not package. For non-BSP cores that are
>> +        * within a building block, enable turbo. The cores within the BSP's
>> +        * building block will just see it already enabled and move on.
>> +        */
>> +       if (lapicid())
>> +               turbo_enable();
>> +
>> +       /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
>> +       msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f080f, 0xe0008),
>> +       msr_clrsetbits_64(MSR_POWER_MISC,
>> +                         ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK, 0);
>> +
>> +       /* Disable C1E */
>> +       msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);
>> +       msr_setbits_64(MSR_POWER_MISC, 0x44);
>> +
>> +       /* Set this core to max frequency ratio */
>> +       braswell_set_max_freq();
>> +
>> +       return 0;
>> +}
>> +
>> +static const struct udevice_id braswell_ids[] = {
>> +       { .compatible = "intel,braswell-cpu" },
>> +       { }
>> +};
>> +
>> +static const struct cpu_ops braswell_ops = {
>> +       .get_desc       = cpu_x86_get_desc,
>> +       .get_info       = braswell_get_info,
>> +       .get_count      = braswell_get_count,
>> +       .get_vendor     = cpu_x86_get_vendor,
>> +};
>> +
>> +U_BOOT_DRIVER(cpu_x86_braswell_drv) = {
>> +       .name           = "cpu_x86_braswell",
>> +       .id             = UCLASS_CPU,
>> +       .of_match       = braswell_ids,
>> +       .bind           = cpu_x86_bind,
>> +       .probe          = braswell_probe,
>> +       .ops            = &braswell_ops,
>> +};
>> diff --git a/arch/x86/cpu/braswell/early_uart.c b/arch/x86/cpu/braswell/early_uart.c
>> new file mode 100644
>> index 0000000..0300e13
>> --- /dev/null
>> +++ b/arch/x86/cpu/braswell/early_uart.c
>> @@ -0,0 +1,86 @@
>> +/*
>> + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
>> + *
>> + * SPDX-License-Identifier:    GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/io.h>
>> +
>> +#define PCI_DEV_CONFIG(segbus, dev, fn) ( \
>> +               (((segbus) & 0xfff) << 20) | \
>> +               (((dev) & 0x1f) << 15) | \
>> +               (((fn)  & 0x07) << 12))
>
> This seems to be shared by baytrail? Do you think it should go in a header file?
>

Yes, I think so.

>> +
>> +/* Platform Controller Unit */
>> +#define LPC_DEV                        0x1f
>> +#define LPC_FUNC               0
>> +
>> +/* Enable UART */
>> +#define UART_CONT              0x80
>> +
>> +/* UART PAD definitions */
>> +#define UART_RXD_COMMUITY      1
>> +#define UART_TXD_COMMUITY      1
>> +#define UART_RXD_FAMILY                4
>> +#define UART_TXD_FAMILY                4
>> +#define UART_RXD_PAD           2
>> +#define UART_TXD_PAD           7
>> +#define UART_RXD_FUNC          3
>> +#define UART_TXD_FUNC          3
>> +
>> +/* IO Memory */
>> +#define IO_BASE_ADDRESS                0xfed80000
>> +
>> +static inline uint32_t gpio_pconf0(int community, int family, int pad)
>> +{
>> +       return IO_BASE_ADDRESS + community * 0x8000 + 0x4400 +
>> +               family * 0x400 + pad * 8;
>> +}
>> +
>> +static void gpio_select_func(int community, int family, int pad, int func)
>> +{
>> +       uint32_t reg;
>> +       uint32_t pconf0_addr = gpio_pconf0(community, family, pad);
>> +
>> +       reg = readl(pconf0_addr);
>> +       reg &= ~(0xf << 16);
>> +       reg |= (func << 16);
>> +       writel(reg, pconf0_addr);
>
> Can we use setclrbits_le32()?

Will do in v2.

>
>> +}
>> +
>> +static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
>> +{
>> +       unsigned long addr;
>> +
>> +       addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
>> +       writel(value, addr);
>> +}
>> +

Regards,
Bin

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 11/13] x86: braswell: Add FSP configuration
  2017-08-26 13:39   ` Simon Glass
@ 2017-08-26 13:56     ` Bin Meng
  2017-08-26 22:39       ` Simon Glass
  2017-09-16  4:32     ` Bin Meng
  1 sibling, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-26 13:56 UTC (permalink / raw
  To: u-boot

Hi Simon,

On Sat, Aug 26, 2017 at 9:39 PM, Simon Glass <sjg@chromium.org> wrote:
> On 15 August 2017 at 23:42, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Add FSP related configuration for Braswell.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/braswell/Makefile                     |   2 +-
>>  arch/x86/cpu/braswell/fsp_configs.c                | 158 ++++++++++++++
>>  .../include/asm/arch-braswell/fsp/fsp_configs.h    |  89 ++++++++
>>  arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h   | 172 +++++++++++++++
>>  arch/x86/include/asm/arch-braswell/gpio.h          | 234 +++++++++++++++++++++
>>  5 files changed, 654 insertions(+), 1 deletion(-)
>>  create mode 100644 arch/x86/cpu/braswell/fsp_configs.c
>>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
>>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
>>  create mode 100644 arch/x86/include/asm/arch-braswell/gpio.h
>>
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> Can this use drivers instead of manual device-tree access?

Which part?

Regards,
Bin

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 11/13] x86: braswell: Add FSP configuration
  2017-08-26 13:56     ` Bin Meng
@ 2017-08-26 22:39       ` Simon Glass
  2017-08-27  0:10         ` Bin Meng
  0 siblings, 1 reply; 47+ messages in thread
From: Simon Glass @ 2017-08-26 22:39 UTC (permalink / raw
  To: u-boot

Hi Bin,

On 26 August 2017 at 07:56, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Sat, Aug 26, 2017 at 9:39 PM, Simon Glass <sjg@chromium.org> wrote:
>> On 15 August 2017 at 23:42, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> Add FSP related configuration for Braswell.
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> ---
>>>
>>>  arch/x86/cpu/braswell/Makefile                     |   2 +-
>>>  arch/x86/cpu/braswell/fsp_configs.c                | 158 ++++++++++++++
>>>  .../include/asm/arch-braswell/fsp/fsp_configs.h    |  89 ++++++++
>>>  arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h   | 172 +++++++++++++++
>>>  arch/x86/include/asm/arch-braswell/gpio.h          | 234 +++++++++++++++++++++
>>>  5 files changed, 654 insertions(+), 1 deletion(-)
>>>  create mode 100644 arch/x86/cpu/braswell/fsp_configs.c
>>>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
>>>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
>>>  create mode 100644 arch/x86/include/asm/arch-braswell/gpio.h
>>>
>>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>
>> Can this use drivers instead of manual device-tree access?
>
> Which part?

Well you have intel,braswell-fsp for example. You could create a
driver with the two compatible strings and have it read the platdata
from the DT in the ofdata_to_platdata() method.

Regards,
Simon

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 11/13] x86: braswell: Add FSP configuration
  2017-08-26 22:39       ` Simon Glass
@ 2017-08-27  0:10         ` Bin Meng
  2017-09-06  1:39           ` Simon Glass
  0 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-08-27  0:10 UTC (permalink / raw
  To: u-boot

Hi Simon,

On Sun, Aug 27, 2017 at 6:39 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 26 August 2017 at 07:56, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Sat, Aug 26, 2017 at 9:39 PM, Simon Glass <sjg@chromium.org> wrote:
>>> On 15 August 2017 at 23:42, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>> Add FSP related configuration for Braswell.
>>>>
>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>>> ---
>>>>
>>>>  arch/x86/cpu/braswell/Makefile                     |   2 +-
>>>>  arch/x86/cpu/braswell/fsp_configs.c                | 158 ++++++++++++++
>>>>  .../include/asm/arch-braswell/fsp/fsp_configs.h    |  89 ++++++++
>>>>  arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h   | 172 +++++++++++++++
>>>>  arch/x86/include/asm/arch-braswell/gpio.h          | 234 +++++++++++++++++++++
>>>>  5 files changed, 654 insertions(+), 1 deletion(-)
>>>>  create mode 100644 arch/x86/cpu/braswell/fsp_configs.c
>>>>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
>>>>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
>>>>  create mode 100644 arch/x86/include/asm/arch-braswell/gpio.h
>>>>
>>>
>>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>>
>>> Can this use drivers instead of manual device-tree access?
>>
>> Which part?
>
> Well you have intel,braswell-fsp for example. You could create a
> driver with the two compatible strings and have it read the platdata
> from the DT in the ofdata_to_platdata() method.

I thought this before. We discussed the possibility of adding a new
FSP uclass long time ago. When I added the Braswell support, I wanted
to have a try since Braswell's FSP is v1.1 spec complaint and if we
have a uclass for FSP we can put the common stuff in the uclass
driver. But in the end I did not do it because:

1. FSP's initialization sequence is just a one time initialization and
we don't do anything after the initialization completes.
2. Making a uclass for FSP means we have to delay fsp_init() to after
initf_dm().But after fsp_init(), we will return to board_init_f()
again and do the initialization for the second time. So all previous
platdata of FSP that is set up by DM gets lost during this process.
3. There are some other architecture-dependent stuff in the
arch_fsp_init() that is not suitable to be put in a FSP driver.

Regards,
Bin

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 01/13] x86: tsc: Add Airmont reference clock values
  2017-08-26 13:38   ` Simon Glass
@ 2017-09-02 16:11     ` Bin Meng
  0 siblings, 0 replies; 47+ messages in thread
From: Bin Meng @ 2017-09-02 16:11 UTC (permalink / raw
  To: u-boot

On Sat, Aug 26, 2017 at 9:38 PM, Simon Glass <sjg@chromium.org> wrote:
> On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Per the Intel 64 and IA-32 Architecture Software Developer's Manual,
>> add the reference clock for Intel Atom Processors based on the Airmont
>> Microarchitecture (Braswell).
>>
>> This keeps in sync with Linux kernel commit:
>>   6fcb41c: x86/tsc_msr: Add Airmont reference clock values
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  drivers/timer/tsc_timer.c | 17 ++++++++++-------
>>  1 file changed, 10 insertions(+), 7 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/next, thanks!

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 02/13] x86: fsp: Update struct common_buf for FSP spec 1.1
  2017-08-26 13:38   ` Simon Glass
@ 2017-09-02 16:11     ` Bin Meng
  0 siblings, 0 replies; 47+ messages in thread
From: Bin Meng @ 2017-09-02 16:11 UTC (permalink / raw
  To: u-boot

On Sat, Aug 26, 2017 at 9:38 PM, Simon Glass <sjg@chromium.org> wrote:
> On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
>> FSP spec 1.1 adds one more member to the struct common_buf to
>> determine the memory size that can be reserved by FSP below "top
>> of low usable memory" for bootloader usage. This new member uses
>> the reserved space so that it is still compatible with previous
>> FSP spec 1.0.
>>
>> A new HOB (FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID) is also
>> published when common_buf.tolum_size is valid and non zero.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/include/asm/fsp/fsp_api.h | 3 ++-
>>  arch/x86/include/asm/fsp/fsp_hob.h | 8 ++++++++
>>  2 files changed, 10 insertions(+), 1 deletion(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/next, thanks!

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 03/13] x86: fsp: Add FSP_GRAPHICS_INFO_HOB
  2017-08-26 13:38   ` Simon Glass
@ 2017-09-02 16:11     ` Bin Meng
  0 siblings, 0 replies; 47+ messages in thread
From: Bin Meng @ 2017-09-02 16:11 UTC (permalink / raw
  To: u-boot

On Sat, Aug 26, 2017 at 9:38 PM, Simon Glass <sjg@chromium.org> wrote:
> On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
>> This adds a new HOB type for graphics information introduced in FSP
>> spec 1.1. When graphics capability is included in FSP and enabled,
>> FSP produces an FSP_GRAPHICS_INFO_HOB as described in the EFI PI
>> specification which provides information about the graphics mode and
>> framebuffer.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/include/asm/fsp/fsp_hob.h     | 26 ++++++++++++++++++++++++++
>>  arch/x86/include/asm/fsp/fsp_support.h | 12 ++++++++++++
>>  arch/x86/lib/fsp/fsp_support.c         |  7 +++++++
>>  3 files changed, 45 insertions(+)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/next, thanks!

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 04/13] x86: Add Video BIOS Table (VBT) related Kconfig options
  2017-08-26 13:38   ` Simon Glass
@ 2017-09-02 16:11     ` Bin Meng
  0 siblings, 0 replies; 47+ messages in thread
From: Bin Meng @ 2017-09-02 16:11 UTC (permalink / raw
  To: u-boot

On Sat, Aug 26, 2017 at 9:38 PM, Simon Glass <sjg@chromium.org> wrote:
> On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
>> This adds Kconfig options for Video BIOS Table which is normally
>> required if you are using an Intel FSP firmware that is complaint
>> with spec 1.1 or later to initialize the integrated graphics device.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/Kconfig | 34 ++++++++++++++++++++++++++++++++++
>>  1 file changed, 34 insertions(+)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/next, thanks!

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 05/13] tools: binman: Add a new entry type for Intel VBT
  2017-08-26 13:38   ` Simon Glass
@ 2017-09-02 16:11     ` Bin Meng
  0 siblings, 0 replies; 47+ messages in thread
From: Bin Meng @ 2017-09-02 16:11 UTC (permalink / raw
  To: u-boot

On Sat, Aug 26, 2017 at 9:38 PM, Simon Glass <sjg@chromium.org> wrote:
> On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
>> This adds a new entry type for Intel Video BIOS Table.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  tools/binman/etype/intel_vbt.py    | 14 ++++++++++++++
>>  tools/binman/func_test.py          |  9 ++++++++-
>>  tools/binman/test/46_intel-vbt.dts | 14 ++++++++++++++
>>  3 files changed, 36 insertions(+), 1 deletion(-)
>>  create mode 100644 tools/binman/etype/intel_vbt.py
>>  create mode 100644 tools/binman/test/46_intel-vbt.dts
>
> Reviewed-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/next, thanks!

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 06/13] x86: dts: Include Intel Video BIOS Table in the ROM image
  2017-08-26 13:39   ` Simon Glass
@ 2017-09-02 16:11     ` Bin Meng
  0 siblings, 0 replies; 47+ messages in thread
From: Bin Meng @ 2017-09-02 16:11 UTC (permalink / raw
  To: u-boot

On Sat, Aug 26, 2017 at 9:39 PM, Simon Glass <sjg@chromium.org> wrote:
> On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Now that binman is able to recognize the Video BIOS Table entry,
>> add such one in the u-boot.dtsi.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/dts/u-boot.dtsi | 6 ++++++
>>  1 file changed, 6 insertions(+)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/next, thanks!

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 07/13] x86: dm: video: Add a framebuffer driver that utilizes VBT
  2017-08-26  3:36   ` Simon Glass
@ 2017-09-02 16:11     ` Bin Meng
  0 siblings, 0 replies; 47+ messages in thread
From: Bin Meng @ 2017-09-02 16:11 UTC (permalink / raw
  To: u-boot

On Sat, Aug 26, 2017 at 11:36 AM, Simon Glass <sjg@chromium.org> wrote:
> On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
>> When a VBT is given to an FSP that supports graphics initialization,
>> the FSP will produce a graphics info HOB that contains all necessary
>> information for the linear frame buffer of the integrated graphics
>> device. This adds a DM video driver for it.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/Kconfig                |   8 +++
>>  arch/x86/lib/fsp/Makefile       |   1 +
>>  arch/x86/lib/fsp/fsp_graphics.c | 124 ++++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 133 insertions(+)
>>  create mode 100644 arch/x86/lib/fsp/fsp_graphics.c
>
> Reviewed-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/next, thanks!

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 08/13] x86: fsp: Update fsp command to show spec 1.1 header
  2017-08-26 13:39   ` Simon Glass
@ 2017-09-02 16:11     ` Bin Meng
  0 siblings, 0 replies; 47+ messages in thread
From: Bin Meng @ 2017-09-02 16:11 UTC (permalink / raw
  To: u-boot

On Sat, Aug 26, 2017 at 9:39 PM, Simon Glass <sjg@chromium.org> wrote:
> On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
>> FSP spec 1.1 adds 3 new APIs and their offsets are in the header.
>> Update the 'fsp hdr' command to show these new entries.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/include/asm/fsp/fsp_infoheader.h |  9 ++++++++-
>>  arch/x86/lib/fsp/cmd_fsp.c                | 24 ++++++++++++++++++++++--
>>  2 files changed, 30 insertions(+), 3 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/next, thanks!

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 11/13] x86: braswell: Add FSP configuration
  2017-08-27  0:10         ` Bin Meng
@ 2017-09-06  1:39           ` Simon Glass
  2017-09-12 15:20             ` Bin Meng
  0 siblings, 1 reply; 47+ messages in thread
From: Simon Glass @ 2017-09-06  1:39 UTC (permalink / raw
  To: u-boot

Hi Bin,

On 26 August 2017 at 18:10, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Sun, Aug 27, 2017 at 6:39 AM, Simon Glass <sjg@chromium.org> wrote:
>> Hi Bin,
>>
>> On 26 August 2017 at 07:56, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> Hi Simon,
>>>
>>> On Sat, Aug 26, 2017 at 9:39 PM, Simon Glass <sjg@chromium.org> wrote:
>>>> On 15 August 2017 at 23:42, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>> Add FSP related configuration for Braswell.
>>>>>
>>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>>>> ---
>>>>>
>>>>>  arch/x86/cpu/braswell/Makefile                     |   2 +-
>>>>>  arch/x86/cpu/braswell/fsp_configs.c                | 158 ++++++++++++++
>>>>>  .../include/asm/arch-braswell/fsp/fsp_configs.h    |  89 ++++++++
>>>>>  arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h   | 172 +++++++++++++++
>>>>>  arch/x86/include/asm/arch-braswell/gpio.h          | 234 +++++++++++++++++++++
>>>>>  5 files changed, 654 insertions(+), 1 deletion(-)
>>>>>  create mode 100644 arch/x86/cpu/braswell/fsp_configs.c
>>>>>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
>>>>>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
>>>>>  create mode 100644 arch/x86/include/asm/arch-braswell/gpio.h
>>>>>
>>>>
>>>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>>>
>>>> Can this use drivers instead of manual device-tree access?
>>>
>>> Which part?
>>
>> Well you have intel,braswell-fsp for example. You could create a
>> driver with the two compatible strings and have it read the platdata
>> from the DT in the ofdata_to_platdata() method.
>
> I thought this before. We discussed the possibility of adding a new
> FSP uclass long time ago. When I added the Braswell support, I wanted
> to have a try since Braswell's FSP is v1.1 spec complaint and if we
> have a uclass for FSP we can put the common stuff in the uclass
> driver. But in the end I did not do it because:
>
> 1. FSP's initialization sequence is just a one time initialization and
> we don't do anything after the initialization completes.

That's not a very good reason though. There will be several drivers like that.

> 2. Making a uclass for FSP means we have to delay fsp_init() to after
> initf_dm().But after fsp_init(), we will return to board_init_f()
> again and do the initialization for the second time. So all previous
> platdata of FSP that is set up by DM gets lost during this process.

Yes, although this is in the nature of the broken FSP API that we hope
Intel will fix. As I understand it we already do the init twice, this
is just a case of knowing what stage we are at.

> 3. There are some other architecture-dependent stuff in the
> arch_fsp_init() that is not suitable to be put in a FSP driver.

But I am suggesting having a driver specific to the arch, not a
generic one, so this should not be a problem.

Regards,
Simon

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 11/13] x86: braswell: Add FSP configuration
  2017-09-06  1:39           ` Simon Glass
@ 2017-09-12 15:20             ` Bin Meng
  2017-09-13  2:31               ` Simon Glass
  0 siblings, 1 reply; 47+ messages in thread
From: Bin Meng @ 2017-09-12 15:20 UTC (permalink / raw
  To: u-boot

Hi Simon,

On Wed, Sep 6, 2017 at 9:39 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 26 August 2017 at 18:10, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Sun, Aug 27, 2017 at 6:39 AM, Simon Glass <sjg@chromium.org> wrote:
>>> Hi Bin,
>>>
>>> On 26 August 2017 at 07:56, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>> Hi Simon,
>>>>
>>>> On Sat, Aug 26, 2017 at 9:39 PM, Simon Glass <sjg@chromium.org> wrote:
>>>>> On 15 August 2017 at 23:42, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>>> Add FSP related configuration for Braswell.
>>>>>>
>>>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>>>>> ---
>>>>>>
>>>>>>  arch/x86/cpu/braswell/Makefile                     |   2 +-
>>>>>>  arch/x86/cpu/braswell/fsp_configs.c                | 158 ++++++++++++++
>>>>>>  .../include/asm/arch-braswell/fsp/fsp_configs.h    |  89 ++++++++
>>>>>>  arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h   | 172 +++++++++++++++
>>>>>>  arch/x86/include/asm/arch-braswell/gpio.h          | 234 +++++++++++++++++++++
>>>>>>  5 files changed, 654 insertions(+), 1 deletion(-)
>>>>>>  create mode 100644 arch/x86/cpu/braswell/fsp_configs.c
>>>>>>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
>>>>>>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
>>>>>>  create mode 100644 arch/x86/include/asm/arch-braswell/gpio.h
>>>>>>
>>>>>
>>>>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>>>>
>>>>> Can this use drivers instead of manual device-tree access?
>>>>
>>>> Which part?
>>>
>>> Well you have intel,braswell-fsp for example. You could create a
>>> driver with the two compatible strings and have it read the platdata
>>> from the DT in the ofdata_to_platdata() method.
>>
>> I thought this before. We discussed the possibility of adding a new
>> FSP uclass long time ago. When I added the Braswell support, I wanted
>> to have a try since Braswell's FSP is v1.1 spec complaint and if we
>> have a uclass for FSP we can put the common stuff in the uclass
>> driver. But in the end I did not do it because:
>>
>> 1. FSP's initialization sequence is just a one time initialization and
>> we don't do anything after the initialization completes.
>
> That's not a very good reason though. There will be several drivers like that.
>
>> 2. Making a uclass for FSP means we have to delay fsp_init() to after
>> initf_dm().But after fsp_init(), we will return to board_init_f()
>> again and do the initialization for the second time. So all previous
>> platdata of FSP that is set up by DM gets lost during this process.
>
> Yes, although this is in the nature of the broken FSP API that we hope
> Intel will fix. As I understand it we already do the init twice, this
> is just a case of knowing what stage we are at.
>

But DM initialization is unnecessary to get FSP run. This will lead
longer boot time.

>> 3. There are some other architecture-dependent stuff in the
>> arch_fsp_init() that is not suitable to be put in a FSP driver.
>
> But I am suggesting having a driver specific to the arch, not a
> generic one, so this should not be a problem.

I mean there will be some non-FSP driver stuff (eg: MRC cache, ACPI
S3) in the FSP driver, which doesn't look very good IMO.

Regards,
Bin

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 11/13] x86: braswell: Add FSP configuration
  2017-09-12 15:20             ` Bin Meng
@ 2017-09-13  2:31               ` Simon Glass
  0 siblings, 0 replies; 47+ messages in thread
From: Simon Glass @ 2017-09-13  2:31 UTC (permalink / raw
  To: u-boot

Hi Bin,

On 12 September 2017 at 09:20, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Wed, Sep 6, 2017 at 9:39 AM, Simon Glass <sjg@chromium.org> wrote:
>> Hi Bin,
>>
>> On 26 August 2017 at 18:10, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> Hi Simon,
>>>
>>> On Sun, Aug 27, 2017 at 6:39 AM, Simon Glass <sjg@chromium.org> wrote:
>>>> Hi Bin,
>>>>
>>>> On 26 August 2017 at 07:56, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>> Hi Simon,
>>>>>
>>>>> On Sat, Aug 26, 2017 at 9:39 PM, Simon Glass <sjg@chromium.org> wrote:
>>>>>> On 15 August 2017 at 23:42, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>>>> Add FSP related configuration for Braswell.
>>>>>>>
>>>>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>>>>>> ---
>>>>>>>
>>>>>>>  arch/x86/cpu/braswell/Makefile                     |   2 +-
>>>>>>>  arch/x86/cpu/braswell/fsp_configs.c                | 158 ++++++++++++++
>>>>>>>  .../include/asm/arch-braswell/fsp/fsp_configs.h    |  89 ++++++++
>>>>>>>  arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h   | 172 +++++++++++++++
>>>>>>>  arch/x86/include/asm/arch-braswell/gpio.h          | 234 +++++++++++++++++++++
>>>>>>>  5 files changed, 654 insertions(+), 1 deletion(-)
>>>>>>>  create mode 100644 arch/x86/cpu/braswell/fsp_configs.c
>>>>>>>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
>>>>>>>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
>>>>>>>  create mode 100644 arch/x86/include/asm/arch-braswell/gpio.h
>>>>>>>
>>>>>>
>>>>>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>>>>>
>>>>>> Can this use drivers instead of manual device-tree access?
>>>>>
>>>>> Which part?
>>>>
>>>> Well you have intel,braswell-fsp for example. You could create a
>>>> driver with the two compatible strings and have it read the platdata
>>>> from the DT in the ofdata_to_platdata() method.
>>>
>>> I thought this before. We discussed the possibility of adding a new
>>> FSP uclass long time ago. When I added the Braswell support, I wanted
>>> to have a try since Braswell's FSP is v1.1 spec complaint and if we
>>> have a uclass for FSP we can put the common stuff in the uclass
>>> driver. But in the end I did not do it because:
>>>
>>> 1. FSP's initialization sequence is just a one time initialization and
>>> we don't do anything after the initialization completes.
>>
>> That's not a very good reason though. There will be several drivers like that.
>>
>>> 2. Making a uclass for FSP means we have to delay fsp_init() to after
>>> initf_dm().But after fsp_init(), we will return to board_init_f()
>>> again and do the initialization for the second time. So all previous
>>> platdata of FSP that is set up by DM gets lost during this process.
>>
>> Yes, although this is in the nature of the broken FSP API that we hope
>> Intel will fix. As I understand it we already do the init twice, this
>> is just a case of knowing what stage we are at.
>>
>
> But DM initialization is unnecessary to get FSP run. This will lead
> longer boot time.

Looking at the init sequence in board_f(), we have fsp_init() quite early:

#if defined(CONFIG_HAVE_FSP)
arch_fsp_init,
#endif
arch_cpu_init, /* basic arch cpu dependent setup */
mach_cpu_init, /* SoC/machine dependent CPU setup */
initf_dm,
arch_cpu_init_dm,

I still feel that ultimately FSP should be a driver (and should happen
before arch_cpu_init_dm(), and that this should not affect boot time
(since we need to do DM init at some point), but I think this needs
more investigation. We would need to first empty out arch_cpu_init()
and march_cpu_init().

So for now, let's leave it as is.

>
>>> 3. There are some other architecture-dependent stuff in the
>>> arch_fsp_init() that is not suitable to be put in a FSP driver.
>>
>> But I am suggesting having a driver specific to the arch, not a
>> generic one, so this should not be a problem.
>
> I mean there will be some non-FSP driver stuff (eg: MRC cache, ACPI
> S3) in the FSP driver, which doesn't look very good IMO.

Well given the nature of FSP (whole platform init) I think this is
fine. The FSP driver can call out to common code or pull in other
drivers as needed.

Regards,
Simon

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 09/13] x86: Add Intel Braswell SoC support
  2017-08-26 13:55     ` Bin Meng
@ 2017-09-16  4:32       ` Bin Meng
  0 siblings, 0 replies; 47+ messages in thread
From: Bin Meng @ 2017-09-16  4:32 UTC (permalink / raw
  To: u-boot

On Sat, Aug 26, 2017 at 9:55 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Sat, Aug 26, 2017 at 9:39 PM, Simon Glass <sjg@chromium.org> wrote:
>> On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> This adds initial Intel Braswell SoC support. It uses Intel FSP
>>> to initialize the chipset.
>>>
>>> Similar to its predecessor BayTrail, there are some work to do to
>>> enable the legacy UART integrated in the Braswell SoC.
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> ---
>>>
>>>  arch/x86/Kconfig                           |   1 +
>>>  arch/x86/cpu/Makefile                      |   1 +
>>>  arch/x86/cpu/braswell/Kconfig              |  38 +++++++
>>>  arch/x86/cpu/braswell/Makefile             |   7 ++
>>>  arch/x86/cpu/braswell/braswell.c           |  36 ++++++
>>>  arch/x86/cpu/braswell/cpu.c                | 170 +++++++++++++++++++++++++++++
>>>  arch/x86/cpu/braswell/early_uart.c         |  86 +++++++++++++++
>>>  arch/x86/include/asm/arch-braswell/iomap.h |  50 +++++++++
>>>  8 files changed, 389 insertions(+)
>>>  create mode 100644 arch/x86/cpu/braswell/Kconfig
>>>  create mode 100644 arch/x86/cpu/braswell/Makefile
>>>  create mode 100644 arch/x86/cpu/braswell/braswell.c
>>>  create mode 100644 arch/x86/cpu/braswell/cpu.c
>>>  create mode 100644 arch/x86/cpu/braswell/early_uart.c
>>>  create mode 100644 arch/x86/include/asm/arch-braswell/iomap.h
>>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>
>> A few nits / suggestions below.
>>
>>>

[snip]

>>> +static void gpio_select_func(int community, int family, int pad, int func)
>>> +{
>>> +       uint32_t reg;
>>> +       uint32_t pconf0_addr = gpio_pconf0(community, family, pad);
>>> +
>>> +       reg = readl(pconf0_addr);
>>> +       reg &= ~(0xf << 16);
>>> +       reg |= (func << 16);
>>> +       writel(reg, pconf0_addr);
>>
>> Can we use setclrbits_le32()?
>
> Will do in v2.
>

Changed to use clrsetbits_le32(), and

>>
>>> +}
>>> +
>>> +static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
>>> +{
>>> +       unsigned long addr;
>>> +
>>> +       addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
>>> +       writel(value, addr);
>>> +}
>>> +

applied to u-boot-x86, thanks!

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 10/13] x86: braswell: Add microcode for B0/C0/D0 stepping SoC
  2017-08-26 13:39   ` Simon Glass
@ 2017-09-16  4:32     ` Bin Meng
  0 siblings, 0 replies; 47+ messages in thread
From: Bin Meng @ 2017-09-16  4:32 UTC (permalink / raw
  To: u-boot

On Sat, Aug 26, 2017 at 9:39 PM, Simon Glass <sjg@chromium.org> wrote:
> On 15 August 2017 at 23:41, Bin Meng <bmeng.cn@gmail.com> wrote:
>> This adds microcode device tree fragment for Braswell B0 (406C2),
>> C0 (406C3) and D0 (406C4) stepping SoC.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/dts/microcode/m01406c2220.dtsi | 4308 +++++++++++++++++++++++++++++++
>>  arch/x86/dts/microcode/m01406c3363.dtsi | 4308 +++++++++++++++++++++++++++++++
>>  arch/x86/dts/microcode/m01406c440a.dtsi | 4308 +++++++++++++++++++++++++++++++
>>  3 files changed, 12924 insertions(+)
>>  create mode 100644 arch/x86/dts/microcode/m01406c2220.dtsi
>>  create mode 100644 arch/x86/dts/microcode/m01406c3363.dtsi
>>  create mode 100644 arch/x86/dts/microcode/m01406c440a.dtsi
>
> Reviewed-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86, thanks!

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 11/13] x86: braswell: Add FSP configuration
  2017-08-26 13:39   ` Simon Glass
  2017-08-26 13:56     ` Bin Meng
@ 2017-09-16  4:32     ` Bin Meng
  1 sibling, 0 replies; 47+ messages in thread
From: Bin Meng @ 2017-09-16  4:32 UTC (permalink / raw
  To: u-boot

On Sat, Aug 26, 2017 at 9:39 PM, Simon Glass <sjg@chromium.org> wrote:
> On 15 August 2017 at 23:42, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Add FSP related configuration for Braswell.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/braswell/Makefile                     |   2 +-
>>  arch/x86/cpu/braswell/fsp_configs.c                | 158 ++++++++++++++
>>  .../include/asm/arch-braswell/fsp/fsp_configs.h    |  89 ++++++++
>>  arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h   | 172 +++++++++++++++
>>  arch/x86/include/asm/arch-braswell/gpio.h          | 234 +++++++++++++++++++++
>>  5 files changed, 654 insertions(+), 1 deletion(-)
>>  create mode 100644 arch/x86/cpu/braswell/fsp_configs.c
>>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
>>  create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
>>  create mode 100644 arch/x86/include/asm/arch-braswell/gpio.h
>>
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>

applied to u-boot-x86, thanks!

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 12/13] x86: braswell: Disable PUNIT power configuration for B0 stepping
  2017-08-26 13:39   ` Simon Glass
@ 2017-09-16  4:32     ` Bin Meng
  0 siblings, 0 replies; 47+ messages in thread
From: Bin Meng @ 2017-09-16  4:32 UTC (permalink / raw
  To: u-boot

On Sat, Aug 26, 2017 at 9:39 PM, Simon Glass <sjg@chromium.org> wrote:
> On 15 August 2017 at 23:42, Bin Meng <bmeng.cn@gmail.com> wrote:
>> FSP's built-in UPD configuration enables PUNIT power configuration,
>> but on B0 stepping, this causes CPU hangs in fsp_init(). Disable it.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/braswell/fsp_configs.c | 6 ++++++
>>  1 file changed, 6 insertions(+)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86, thanks!

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [U-Boot] [PATCH 13/13] x86: Support Intel Cherry Hill board
  2017-08-26 13:39   ` Simon Glass
@ 2017-09-16  4:32     ` Bin Meng
  0 siblings, 0 replies; 47+ messages in thread
From: Bin Meng @ 2017-09-16  4:32 UTC (permalink / raw
  To: u-boot

On Sat, Aug 26, 2017 at 9:39 PM, Simon Glass <sjg@chromium.org> wrote:
> On 15 August 2017 at 23:42, Bin Meng <bmeng.cn@gmail.com> wrote:
>> This adds support to Intel Cherry Hill board, a board based on
>> Intel Braswell SoC. The following devices are validated:
>>
>> - serial port as the serial console
>> - on-board Realtek 8169 ethernet controller
>> - SATA AHCI controller
>> - EMMC/SDHC controller
>> - USB 3.0 xHCI controller
>> - PCIe x1 slot with a graphics card
>> - ICH SPI controller with an 8MB Macronix SPI flash
>> - Integrated graphics device as the video console
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>
>> ---
>>
>>  arch/x86/dts/Makefile               |   1 +
>>  arch/x86/dts/cherryhill.dts         | 215 +++++++++++++
>>  board/intel/Kconfig                 |  10 +
>>  board/intel/cherryhill/Kconfig      |  25 ++
>>  board/intel/cherryhill/MAINTAINERS  |   6 +
>>  board/intel/cherryhill/Makefile     |   7 +
>>  board/intel/cherryhill/cherryhill.c | 596 ++++++++++++++++++++++++++++++++++++
>>  board/intel/cherryhill/start.S      |   9 +
>>  configs/cherryhill_defconfig        |  36 +++
>>  doc/README.x86                      |  30 ++
>>  include/configs/cherryhill.h        |  22 ++
>>  11 files changed, 957 insertions(+)
>>  create mode 100644 arch/x86/dts/cherryhill.dts
>>  create mode 100644 board/intel/cherryhill/Kconfig
>>  create mode 100644 board/intel/cherryhill/MAINTAINERS
>>  create mode 100644 board/intel/cherryhill/Makefile
>>  create mode 100644 board/intel/cherryhill/cherryhill.c
>>  create mode 100644 board/intel/cherryhill/start.S
>>  create mode 100644 configs/cherryhill_defconfig
>>  create mode 100644 include/configs/cherryhill.h
>
> Reviewed-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86, thanks!

^ permalink raw reply	[flat|nested] 47+ messages in thread

end of thread, other threads:[~2017-09-16  4:32 UTC | newest]

Thread overview: 47+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-08-16  5:41 [U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support Bin Meng
2017-08-16  5:41 ` [U-Boot] [PATCH 01/13] x86: tsc: Add Airmont reference clock values Bin Meng
2017-08-26 13:38   ` Simon Glass
2017-09-02 16:11     ` Bin Meng
2017-08-16  5:41 ` [U-Boot] [PATCH 02/13] x86: fsp: Update struct common_buf for FSP spec 1.1 Bin Meng
2017-08-26 13:38   ` Simon Glass
2017-09-02 16:11     ` Bin Meng
2017-08-16  5:41 ` [U-Boot] [PATCH 03/13] x86: fsp: Add FSP_GRAPHICS_INFO_HOB Bin Meng
2017-08-26 13:38   ` Simon Glass
2017-09-02 16:11     ` Bin Meng
2017-08-16  5:41 ` [U-Boot] [PATCH 04/13] x86: Add Video BIOS Table (VBT) related Kconfig options Bin Meng
2017-08-26 13:38   ` Simon Glass
2017-09-02 16:11     ` Bin Meng
2017-08-16  5:41 ` [U-Boot] [PATCH 05/13] tools: binman: Add a new entry type for Intel VBT Bin Meng
2017-08-26 13:38   ` Simon Glass
2017-09-02 16:11     ` Bin Meng
2017-08-16  5:41 ` [U-Boot] [PATCH 06/13] x86: dts: Include Intel Video BIOS Table in the ROM image Bin Meng
2017-08-26 13:39   ` Simon Glass
2017-09-02 16:11     ` Bin Meng
2017-08-16  5:41 ` [U-Boot] [PATCH 07/13] x86: dm: video: Add a framebuffer driver that utilizes VBT Bin Meng
2017-08-26  3:36   ` Simon Glass
2017-09-02 16:11     ` Bin Meng
2017-08-16  5:41 ` [U-Boot] [PATCH 08/13] x86: fsp: Update fsp command to show spec 1.1 header Bin Meng
2017-08-26 13:39   ` Simon Glass
2017-09-02 16:11     ` Bin Meng
2017-08-16  5:41 ` [U-Boot] [PATCH 09/13] x86: Add Intel Braswell SoC support Bin Meng
2017-08-26 13:39   ` Simon Glass
2017-08-26 13:55     ` Bin Meng
2017-09-16  4:32       ` Bin Meng
2017-08-16  5:41 ` [U-Boot] [PATCH 10/13] x86: braswell: Add microcode for B0/C0/D0 stepping SoC Bin Meng
2017-08-26 13:39   ` Simon Glass
2017-09-16  4:32     ` Bin Meng
2017-08-16  5:42 ` [U-Boot] [PATCH 11/13] x86: braswell: Add FSP configuration Bin Meng
2017-08-26 13:39   ` Simon Glass
2017-08-26 13:56     ` Bin Meng
2017-08-26 22:39       ` Simon Glass
2017-08-27  0:10         ` Bin Meng
2017-09-06  1:39           ` Simon Glass
2017-09-12 15:20             ` Bin Meng
2017-09-13  2:31               ` Simon Glass
2017-09-16  4:32     ` Bin Meng
2017-08-16  5:42 ` [U-Boot] [PATCH 12/13] x86: braswell: Disable PUNIT power configuration for B0 stepping Bin Meng
2017-08-26 13:39   ` Simon Glass
2017-09-16  4:32     ` Bin Meng
2017-08-16  5:42 ` [U-Boot] [PATCH 13/13] x86: Support Intel Cherry Hill board Bin Meng
2017-08-26 13:39   ` Simon Glass
2017-09-16  4:32     ` Bin Meng

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