From: Kever Yang <kever.yang@rock-chips.com>
To: Jonas Karlman <jonas@kwiboo.se>, Simon Glass <sjg@chromium.org>,
Lukasz Majewski <lukma@denx.de>,
Sean Anderson <seanga2@gmail.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Tom Rini <trini@konsulko.com>
Cc: u-boot@lists.denx.de
Subject: Re: [PATCH] clk: rockchip: rk3328: Add SCLK_USB3OTG_REF support
Date: Tue, 7 May 2024 11:28:03 +0800 [thread overview]
Message-ID: <51603d40-ee6b-499a-9576-bacb07e91551@rock-chips.com> (raw)
In-Reply-To: <20240501192352.962891-1-jonas@kwiboo.se>
On 2024/5/2 03:23, Jonas Karlman wrote:
> The SCLK_USB3OTG_REF clocks is used as reference clock for USB3 block.
>
> Add simple support to get rate of SCLK_USB3OTG_REF clocks to fix
> reference clock period configuration.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> This has been runtime tested on a Rock64 and NanoPi R2S Plus.
> ---
> drivers/clk/rockchip/clk_rk3328.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
> index 87075ec71340..314b903eaa03 100644
> --- a/drivers/clk/rockchip/clk_rk3328.c
> +++ b/drivers/clk/rockchip/clk_rk3328.c
> @@ -706,6 +706,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
> case PCLK_HDMIPHY:
> rate = rk3328_hdmiphy_get_clk(priv->cru);
> break;
> + case SCLK_USB3OTG_REF:
> + rate = OSC_HZ;
> + break;
> default:
> return -ENOENT;
> }
> @@ -780,6 +783,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
> case PCLK_DDR:
> case ACLK_GMAC:
> case PCLK_GMAC:
> + case SCLK_USB3OTG_REF:
> case SCLK_USB3OTG_SUSPEND:
> case USB480M:
> return 0;
prev parent reply other threads:[~2024-05-07 3:28 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-01 19:23 [PATCH] clk: rockchip: rk3328: Add SCLK_USB3OTG_REF support Jonas Karlman
2024-05-07 3:28 ` Kever Yang [this message]
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