From: "Alvin Che-Chia Chang(張哲嘉)" <alvinga@andestech.com>
To: "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "alistair.francis@wdc.com" <alistair.francis@wdc.com>,
"bin.meng@windriver.com" <bin.meng@windriver.com>,
"liwei1518@gmail.com" <liwei1518@gmail.com>,
"dbarboza@ventanamicro.com" <dbarboza@ventanamicro.com>,
"zhiwei_liu@linux.alibaba.com" <zhiwei_liu@linux.alibaba.com>
Subject: RE: [PATCH v4 0/4] RISC-V: Modularize common match conditions for trigger
Date: Thu, 7 Mar 2024 02:35:21 +0000 [thread overview]
Message-ID: <SEYPR03MB6700853CCA2198D3E7DA7E7DA8202@SEYPR03MB6700.apcprd03.prod.outlook.com> (raw)
In-Reply-To: <20240227012405.71650-1-alvinga@andestech.com>
Hi Alistair,
Please also take a look at this series, I guess it is ready to be applied, thanks!
BRs,
Alvin
> -----Original Message-----
> From: Alvin Che-Chia Chang(張哲嘉) <alvinga@andestech.com>
> Sent: Tuesday, February 27, 2024 9:24 AM
> To: qemu-riscv@nongnu.org; qemu-devel@nongnu.org
> Cc: alistair.francis@wdc.com; bin.meng@windriver.com;
> liwei1518@gmail.com; dbarboza@ventanamicro.com;
> zhiwei_liu@linux.alibaba.com; Alvin Che-Chia Chang(張哲嘉)
> <alvinga@andestech.com>
> Subject: [PATCH v4 0/4] RISC-V: Modularize common match conditions for
> trigger
>
> According to RISC-V Debug specification ratified version 0.13 [1] (also applied
> to version 1.0 [2] but it has not been ratified yet), the enabled privilege levels
> of the trigger is common match conditions for all the types of the trigger.
>
> This series modularize the code for checking the privilege levels of type 2/3/6
> triggers by implementing functions trigger_common_match() and
> trigger_priv_match().
>
> Additional match conditions, such as CSR tcontrol and textra, can be further
> implemented into trigger_common_match() in the future.
>
> [1]: https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote
> [2]: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-asciidoc
>
> Changes from v3:
> - Change this series to target Debug Spec. version 0.13
>
> Changes from v2:
> - Explicitly mention the targeting version of RISC-V Debug Spec.
>
> Changes from v1:
> - Fix typo
> - Add commit description for changing behavior of looping the triggers
> when we check type 2 triggers.
>
> Alvin Chang (4):
> target/riscv: Add functions for common matching conditions of trigger
> target/riscv: Apply modularized matching conditions for breakpoint
> target/riscv: Apply modularized matching conditions for watchpoint
> target/riscv: Apply modularized matching conditions for icount trigger
>
> target/riscv/debug.c | 124 +++++++++++++++++++++++++++++--------------
> 1 file changed, 83 insertions(+), 41 deletions(-)
>
> --
> 2.34.1
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next prev parent reply other threads:[~2024-03-07 2:36 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-27 1:24 [PATCH v4 0/4] RISC-V: Modularize common match conditions for trigger Alvin Chang via
2024-02-27 1:24 ` [PATCH v4 1/4] target/riscv: Add functions for common matching conditions of trigger Alvin Chang via
2024-06-04 0:28 ` Alistair Francis
2024-02-27 1:24 ` [PATCH v4 2/4] target/riscv: Apply modularized matching conditions for breakpoint Alvin Chang via
2024-02-27 1:24 ` [PATCH v4 3/4] target/riscv: Apply modularized matching conditions for watchpoint Alvin Chang via
2024-06-04 0:27 ` Alistair Francis
2024-02-27 1:24 ` [PATCH v4 4/4] target/riscv: Apply modularized matching conditions for icount trigger Alvin Chang via
2024-06-04 0:27 ` Alistair Francis
2024-03-07 2:35 ` Alvin Che-Chia Chang(張哲嘉) [this message]
2024-06-04 1:58 ` [PATCH v4 0/4] RISC-V: Modularize common match conditions for trigger Alistair Francis
2024-06-04 4:24 ` Alvin Che-Chia Chang(張哲嘉)
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