From: Alistair Francis <alistair23@gmail.com>
To: Himanshu Chauhan <hchauhan@ventanamicro.com>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, ajones@ventanamicro.com
Subject: Re: [PATCH v7 3/4] target/riscv: Expose sdtrig ISA extension
Date: Mon, 29 Apr 2024 15:41:07 +1000 [thread overview]
Message-ID: <CAKmqyKO67qjXhxRM_j6DP+uu7SzXPACGbCZaFQmUVJ7gv1tC0w@mail.gmail.com> (raw)
In-Reply-To: <20240314185957.36940-4-hchauhan@ventanamicro.com>
On Fri, Mar 15, 2024 at 5:02 AM Himanshu Chauhan
<hchauhan@ventanamicro.com> wrote:
>
> This patch adds "sdtrig" in the ISA string when sdtrig extension is enabled.
> The sdtrig extension may or may not be implemented in a system. Therefore, the
> -cpu rv64,sdtrig=<true/false>
> option can be used to dynamically turn sdtrig extension on or off.
>
> By default, the sdtrig extension is disabled and debug property enabled as usual.
>
> Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ab631500ac..4231f36c1b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -175,6 +175,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
> ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
> ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
> + ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig),
> ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
> ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
> ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
> @@ -1485,6 +1486,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false),
> MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
>
> + MULTI_EXT_CFG_BOOL("sdtrig", ext_sdtrig, false),
> MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false),
> MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
> MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
> --
> 2.34.1
>
>
next prev parent reply other threads:[~2024-04-29 5:42 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-14 18:59 [PATCH v7 0/4] Introduce sdtrig ISA extension Himanshu Chauhan
2024-03-14 18:59 ` [PATCH v7 1/4] target/riscv: Check for valid itimer pointer before free Himanshu Chauhan
2024-04-29 4:04 ` Alistair Francis
2024-03-14 18:59 ` [PATCH v7 2/4] target/riscv: Enable mcontrol6 triggers only when sdtrig is selected Himanshu Chauhan
2024-03-14 19:29 ` Andrew Jones
2024-04-29 4:08 ` Alistair Francis
2024-03-14 18:59 ` [PATCH v7 3/4] target/riscv: Expose sdtrig ISA extension Himanshu Chauhan
2024-03-14 19:30 ` Andrew Jones
2024-04-29 5:41 ` Alistair Francis [this message]
2024-03-14 18:59 ` [PATCH v7 4/4] target/riscv: Enable sdtrig for Ventana's Veyron CPUs Himanshu Chauhan
2024-03-14 19:31 ` Andrew Jones
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