From: Fea Wang <fea.wang@sifive.com>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
Weiwei Li <liwei1518@gmail.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Jim Shu <jim.shu@sifive.com>,
Frank Chang <frank.chang@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Max Chou <max.chou@sifive.com>
Subject: Re: [PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string
Date: Wed, 15 May 2024 15:46:04 +0800 [thread overview]
Message-ID: <CAKhCfse2OvqSuTqrJ3g8dWaPnCWk-BGWZ8TNe17vbPLs9-6AEQ@mail.gmail.com> (raw)
In-Reply-To: <fb91965c-6ff8-4dda-98cc-04668dbd2af4@linux.alibaba.com>
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Thank you, I will correct it in the patch v2.
Sincerely,
Fea
LIU Zhiwei <zhiwei_liu@linux.alibaba.com> 於 2024年5月13日 週一 上午10:55寫道：
>
> On 2024/5/10 14:58, Fea.Wang wrote:
> > From: Jim Shu <jim.shu@sifive.com>
> >
> > Public the conversion function of priv_spec and string in cpu.h, so that
> > tcg-cpu.c could also use it.
> >
> > Signed-off-by: Jim Shu <jim.shu@sifive.com>
> > Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> > Reviewed-by: Frank Chang <frank.chang@sifive.com>
> > ---
> > target/riscv/cpu.c | 4 ++--
> > target/riscv/cpu.h | 3 +++
> > target/riscv/tcg/tcg-cpu.c | 13 +++++--------
> > 3 files changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index a74f0eb29c..b6b48e5620 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -1769,7 +1769,7 @@ static const PropertyInfo prop_pmp = {
> > .set = prop_pmp_set,
> > };
> >
> > -static int priv_spec_from_str(const char *priv_spec_str)
> > +int priv_spec_from_str(const char *priv_spec_str)
> > {
> > int priv_version = -1;
> >
> > @@ -1784,7 +1784,7 @@ static int priv_spec_from_str(const char
> *priv_spec_str)
> > return priv_version;
> > }
> >
> > -static const char *priv_spec_to_str(int priv_version)
> > +const char *priv_spec_to_str(int priv_version)
> > {
> > switch (priv_version) {
> > case PRIV_VERSION_1_10_0:
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index e0dd1828b5..7696102697 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -829,4 +829,7 @@ target_ulong riscv_new_csr_seed(target_ulong
> new_value,
> > uint8_t satp_mode_max_from_map(uint32_t map);
> > const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
> >
> > +const char *priv_spec_to_str(int priv_version);
> > +int priv_spec_from_str(const char *priv_spec_str);
> > +
> > #endif /* RISCV_CPU_H */
> > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> > index 4ebebebe09..faa8de9b83 100644
> > --- a/target/riscv/tcg/tcg-cpu.c
> > +++ b/target/riscv/tcg/tcg-cpu.c
> > @@ -76,16 +76,13 @@ static void riscv_cpu_write_misa_bit(RISCVCPU *cpu,
> uint32_t bit,
> >
> > static const char *cpu_priv_ver_to_str(int priv_ver)
> > {
> > - switch (priv_ver) {
> > - case PRIV_VERSION_1_10_0:
> > - return "v1.10.0";
> > - case PRIV_VERSION_1_11_0:
> > - return "v1.11.0";
> > - case PRIV_VERSION_1_12_0:
> > - return "v1.12.0";
> > + const char *priv_spec_str = priv_spec_to_str(priv_ver);
> > +
> > + if (priv_spec_str == NULL) {
> > + g_assert_not_reached();
> > }
>
> g_assert(priv_spec_str != NULL) or g_assert(priv_spec_str)
>
> Otherwise,
>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>
> Zhiwei
>
> >
> > - g_assert_not_reached();
> > + return priv_spec_str;
> > }
> >
> > static void riscv_cpu_synchronize_from_tb(CPUState *cs,
>
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next prev parent reply other threads:[~2024-05-15 7:47 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-10 6:58 [PATCH 0/5] target/riscv: Support RISC-V privilege 1.13 spec Fea.Wang
2024-05-10 6:58 ` [PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string Fea.Wang
2024-05-11 14:41 ` liwei
2024-05-13 2:54 ` LIU Zhiwei
2024-05-15 7:46 ` Fea Wang [this message]
2024-05-10 6:58 ` [PATCH 2/5] target/riscv: Support the version for ss1p13 Fea.Wang
2024-05-11 14:42 ` liwei
2024-05-13 2:52 ` LIU Zhiwei
2024-05-10 6:58 ` [PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0 Fea.Wang
2024-05-11 14:46 ` liwei
2024-05-13 2:51 ` LIU Zhiwei
2024-05-15 7:46 ` Fea Wang
2024-05-10 6:58 ` [PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 Fea.Wang
2024-05-13 2:48 ` LIU Zhiwei
2024-05-15 7:47 ` Fea Wang
2024-05-10 6:58 ` [PATCH 5/5] target/riscv: Reserve exception codes for sw-check and hw-err Fea.Wang
2024-05-13 2:43 ` LIU Zhiwei
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