messages from 2021-05-12 06:00:12 to 2021-06-10 08:00:29 UTC [more...]
[PATCH v2 00/37] target/riscv: support packed extension v0.9.4
2021-06-10 7:58 UTC (3+ messages)
` [PATCH v2 01/37] target/riscv: implementation-defined constant parameters
` [PATCH v2 02/37] target/riscv: Make the vector helper functions public
TCG op for 32 bit only cpu on qemu-riscv64
2021-06-10 1:43 UTC (6+ messages)
[PATCH v2 0/3] hw/riscv: OpenTitan: Add support for the RISC-V timer
2021-06-09 7:57 UTC (7+ messages)
` [PATCH v2 1/3] hw/char/ibex_uart: Make the register layout private
` [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer
` [PATCH v2 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
[PATCH v16 13/99] meson: add target_user_arch
2021-06-05 22:33 UTC (4+ messages)
` [PATCH v16 93/99] meson: Introduce target-specific Kconfig
[PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
2021-06-05 18:59 UTC (6+ messages)
[PATCH v1 0/3] hw/riscv: OpenTitan: Add support for the RISC-V timer
2021-06-04 2:41 UTC (14+ messages)
` [PATCH v1 1/3] hw/char/ibex_uart: Make the register layout private
` [PATCH v1 2/3] hw/timer: Initial commit of Ibex Timer
` [PATCH v1 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
[PATCH v2 00/12] hw: Various Kconfig fixes
2021-06-03 16:40 UTC (34+ messages)
` [PATCH v2 01/12] hw/mem/nvdimm: Use Kconfig 'imply' instead of 'depends on'
` [PATCH v2 02/12] hw/ide/Kconfig: Add missing dependency PCI -> IDE_QDEV
` [PATCH v2 03/12] hw/arm/Kconfig: Add missing dependency NPCM7XX -> SMBUS
` [PATCH v2 04/12] hw/arm/Kconfig: Remove unused DS1338 symbol from i.MX25 PDK Board
` [PATCH v2 05/12] hw/arm/Kconfig: Add missing SDHCI symbol to FSL_IMX25
` [PATCH v2 06/12] hw/riscv/Kconfig: Add missing dependency MICROCHIP_PFSOC -> SERIAL
` [PATCH v2 07/12] hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines
` [PATCH v2 08/12] hw/ppc/Kconfig: Add missing dependency E500 -> DS1338 RTC
` [PATCH v2 09/12] hw/pci-host/Kconfig: Add missing dependency MV64361 -> I8259
` [PATCH v2 10/12] hw/isa/vt82c686: Add missing Kconfig dependencies (build error)
` [PATCH v2 11/12] hw/isa/vt82c686: Add missing Kconfig dependency (runtime error)
` [PATCH v2 12/12] hw/ppc/Kconfig: Add dependency PEGASOS2 -> ATI_VGA
[PATCH v3] target/riscv: fix VS interrupts forwarding to HS
2021-06-02 19:14 UTC (7+ messages)
[PATCH 0/2] target/riscv: fix hypervisor exceptions
2021-06-02 19:11 UTC (3+ messages)
` [PATCH 1/2] target/riscv: fix VS interrupts forwarding to HS
` [PATCH 2/2] target/riscv: remove force HS exception
HSS Issue with GCC 10, Qemu Setup for microchip-icicle-kit
2021-06-01 18:36 UTC (10+ messages)
[PATCH v1 1/1] target/riscv: Use target_ulong for the DisasContext misa
2021-06-01 11:45 UTC (2+ messages)
[PATCH v2 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
2021-06-01 6:41 UTC (3+ messages)
[PATCH v2 0/2] QOMify Sifive UART Model
2021-05-31 8:13 UTC (7+ messages)
` [PATCH v2 1/2] hw/char: sifive_uart
` [PATCH v2 2/2] "
[PATCH] target/riscv: hardwire bits in hideleg and hedeleg
2021-05-28 2:00 UTC (5+ messages)
[PATCH 1/1] target/riscv: Fix vsip vsie CSR ops in M and HS mode
2021-05-28 0:32 UTC (3+ messages)
[PATCH v6 00/17] support subsets of bitmanip extension
2021-05-27 22:08 UTC (6+ messages)
` [PATCH v6 11/17] target/riscv: rvb: rotate (left/right)
` [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option
[PATCH v9 0/6] RISC-V Pointer Masking implementation
2021-05-26 17:57 UTC (7+ messages)
` [PATCH v9 1/6] [RISCV_PM] Add J-extension into RISC-V
` [PATCH v9 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
` [PATCH v9 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs
` [PATCH v9 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
` [PATCH v9 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
` [PATCH v9 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
[PATCH v7 00/23] cpu: Introduce SysemuCPUOps structure
2021-05-26 17:47 UTC (32+ messages)
` [PATCH v7 01/23] NOTFORMERGE target/arm: Restrict MTE code to softmmu
` [PATCH v7 02/23] cpu: Restrict target cpu_do_transaction_failed() handlers to sysemu
` [PATCH v7 03/23] cpu: Restrict target cpu_do_unaligned_access() "
` [PATCH v7 04/23] cpu: Remove duplicated 'sysemu/hw_accel.h' header
` [PATCH v7 05/23] cpu: Split as cpu-common / cpu-sysemu
` [PATCH v7 06/23] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
` [PATCH v7 07/23] cpu: Introduce cpu_virtio_is_big_endian()
` [PATCH v7 08/23] cpu: Directly use cpu_write_elf*() fallback handlers in place
` [PATCH v7 09/23] cpu: Directly use get_paging_enabled() "
` [PATCH v7 10/23] cpu: Directly use get_memory_mapping() "
` [PATCH v7 11/23] cpu: Assert DeviceClass::vmsd is NULL on user emulation
` [PATCH v7 12/23] cpu: Rename CPUClass vmsd -> legacy_vmsd
` [PATCH v7 13/23] cpu: Move AVR target vmsd field from CPUClass to DeviceClass
` [PATCH v7 14/23] cpu: Introduce SysemuCPUOps structure
` [PATCH v7 15/23] cpu: Move CPUClass::vmsd to SysemuCPUOps
` [PATCH v7 16/23] cpu: Move CPUClass::virtio_is_big_endian "
` [PATCH v7 17/23] cpu: Move CPUClass::get_crash_info "
` [PATCH v7 18/23] cpu: Move CPUClass::write_elf* "
` [PATCH v7 19/23] cpu: Move CPUClass::asidx_from_attrs "
` [PATCH v7 20/23] cpu: Move CPUClass::get_phys_page_debug "
` [PATCH v7 21/23] cpu: Move CPUClass::get_memory_mapping "
` [PATCH v7 22/23] cpu: Move CPUClass::get_paging_enabled "
` [PATCH v7 23/23] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
[PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction
2021-05-26 6:15 UTC (4+ messages)
[PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions
2021-05-26 5:31 UTC (3+ messages)
[PATCH] target/riscv: Pass the same value to oprsz and maxsz
2021-05-25 22:01 UTC (3+ messages)
[PATCH v1 1/1] target/riscv/pmp: Add assert for ePMP operations
2021-05-25 21:53 UTC (4+ messages)
[PATCH 07/38] target/riscv: SIMD 8-bit Shift Instructions
2021-05-24 4:46 UTC (2+ messages)
[PATCH v2] target/riscv: Dump CSR mscratch/sscratch/satp
2021-05-20 7:20 UTC (2+ messages)
[PATCH] target/riscv: Remove unnecessary riscv_*_names[] declaration
2021-05-20 7:15 UTC (4+ messages)
[PATCH] target/riscv: Remove obsolete 'CPU unmigratable' comment
2021-05-18 6:11 UTC (5+ messages)
[PATCH v6 00/18] cpu: Introduce SysemuCPUOps structure
2021-05-17 5:27 UTC (4+ messages)
` [PATCH v6 08/18] cpu/{avr, lm32, moxie}: Set DeviceClass vmsd field (not CPUClass one)
[PATCH 0/2] QOMify Sifive UART model
2021-05-16 11:13 UTC (4+ messages)
` [PATCH 2/2] QOMify sifive_uart model
[PATCH 0/4] AIA local interrupt CSR support
2021-05-14 14:32 UTC (5+ messages)
` [PATCH 1/4] target/riscv: Add defines for AIA local interrupt CSRs
` [PATCH 2/4] target/riscv: Add CPU feature for AIA CSRs
` [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs
` [PATCH 4/4] hw/riscv: virt: Use AIA INTC compatible string when available
[PATCH 06/10] hw/riscv/Kconfig: Add missing dependency MICROCHIP_PFSOC -> SERIAL
2021-05-14 8:14 UTC (5+ messages)
` [PATCH 07/10] hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines
[PATCH] target/riscv: Dump CSR mscratch/sscratch/satp
2021-05-14 3:18 UTC (3+ messages)
[PATCH v2] target/riscv: fix VS interrupts forwarding to HS
2021-05-13 0:17 UTC (2+ messages)
[PATCH V2 0/2] Proposing custom CSR handling logic
2021-05-12 23:41 UTC (7+ messages)
` [PATCH V2 1/2] Adding premliminary support for custom CSR handling mechanism
[PATCH RESEND v8 0/6] RISC-V Pointer Masking implementation
2021-05-12 5:59 UTC (3+ messages)
` [PATCH v8 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).