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From: Michael Tokarev <mjt@tls.msk.ru>
To: Simeon Krastnikov <Simeon.Krastnikov@imgtec.com>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
	"qemu-trivial@nongnu.org" <qemu-trivial@nongnu.org>,
	Shiva Chen <Shiva.Chen@imgtec.com>
Subject: Re: [PATCH] Fix incorrect disassembly format for certain RISC-V instructions
Date: Wed, 24 Apr 2024 12:08:34 +0300	[thread overview]
Message-ID: <839bfcd0-9470-4112-96a3-2acc19fb4c80@tls.msk.ru> (raw)
In-Reply-To: <LO4P265MB6666B4EBBD3BE5DC8822C85E933D2@LO4P265MB6666.GBRP265.PROD.OUTLOOK.COM>

03.04.2024 12:14, Simeon Krastnikov wrote:
> * The immediate argument to lui/auipc should be an integer in the interval
>   [0x0, 0xfffff]; e.g., 'auipc 0xfffff' and not 'auipc -1'
> * The floating-point rounding mode is the last operand to the function,
>    not the first; e.g., 'fcvt.w.s a0, fa0, rtz' and not 'fcvt.w.s rtz,
> a0, fa0'. Note that fcvt.d.w[u] and fcvt.w[u].d are unaffected by the
> rounding mode and hence it is omitted from their disassembly.
> * When aq and rl are both present, they are not separated by a '.';
>    e.g., 'lr.d.aqrl' and not 'lr.d.aq.rl'.
> 
> Based on the following assembly reference:
> https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md

Can someone from the riscv team review this?

This change isn't "trivial enough" for qemu-trivial, it should be picked up
by the riscv team.  At the very least, it touches too many instructions.

Thanks,

/mjt

next prev parent reply	other threads:[~2024-04-24  9:08 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-02 12:47 [PATCH] Fix incorrect disassembly format for certain RISC-V instructions Simeon Krastnikov
2024-04-03  5:14 ` Michael Tokarev
2024-04-03  8:57   ` Philippe Mathieu-Daudé
2024-04-03  9:14 ` Simeon Krastnikov
2024-04-24  9:08   ` Michael Tokarev [this message]
2024-06-04  1:05   ` Alistair Francis

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