From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH for-9.1 v2 2/2] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
Date: Tue, 16 Apr 2024 16:41:32 -0300 [thread overview]
Message-ID: <20240416194132.1843699-3-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20240416194132.1843699-1-dbarboza@ventanamicro.com>
Privileged spec section 4.1.9 mentions:
"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)
If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then stval will contain the faulting
virtual address."
A similar text is found for mtval in section 3.1.16.
Setting mtval/stval in this scenario is optional, but some softwares read
these regs when handling ebreaks.
Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn_trans/trans_privileged.c.inc | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 620ab54eb0..b89e3bd5b5 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -62,6 +62,10 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
} else {
+ TCGv temp = tcg_temp_new();
+ tcg_gen_movi_tl(temp, ebreak_addr);
+ tcg_gen_st_tl(temp, tcg_env, offsetof(CPURISCVState, badaddr));
+
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
}
return true;
--
2.44.0
next prev parent reply other threads:[~2024-04-16 19:42 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-16 19:41 [PATCH for-9.1 v2 0/2] target/riscv: set (m|s)tval on Daniel Henrique Barboza
2024-04-16 19:41 ` [PATCH for-9.1 v2 1/2] target/riscv/debug: set tval=pc in breakpoint exceptions Daniel Henrique Barboza
2024-04-16 19:41 ` Daniel Henrique Barboza [this message]
2024-04-16 19:58 ` [PATCH for-9.1 v2 2/2] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint Richard Henderson
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