From: Jason Chien <jason.chien@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Jason Chien <jason.chien@sifive.com>,
Frank Chang <frank.chang@sifive.com>,
Max Chou <max.chou@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Richard Henderson <richard.henderson@linaro.org>,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH v2 1/5] target/riscv: Add support for Zve32x extension
Date: Mon, 25 Mar 2024 16:33:35 +0800 [thread overview]
Message-ID: <20240325083346.16656-2-jason.chien@sifive.com> (raw)
In-Reply-To: <20240325083346.16656-1-jason.chien@sifive.com>
Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/tcg/tcg-cpu.c | 16 ++++++++--------
6 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 36e3e5fdaf..851ac7372c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -153,6 +153,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
+ ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index cb750154bd..dce49050c0 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -91,6 +91,7 @@ struct RISCVCPUConfig {
bool ext_zhinx;
bool ext_zhinxmin;
bool ext_zve32f;
+ bool ext_zve32x;
bool ext_zve64f;
bool ext_zve64d;
bool ext_zvbb;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index fc090d729a..b13a50a665 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -72,7 +72,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
*cs_base = 0;
- if (cpu->cfg.ext_zve32f) {
+ if (cpu->cfg.ext_zve32x) {
/*
* If env->vl equals to VLMAX, we can use generic vector operation
* expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 726096444f..d96feea5d3 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -93,7 +93,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
static RISCVException vs(CPURISCVState *env, int csrno)
{
- if (riscv_cpu_cfg(env)->ext_zve32f) {
+ if (riscv_cpu_cfg(env)->ext_zve32x) {
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 7d84e7d812..eec2939e23 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -149,7 +149,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
{
TCGv s1, dst;
- if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
return false;
}
@@ -179,7 +179,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
{
TCGv dst;
- if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
return false;
}
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index b5b95e052d..ff0d485e7f 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -511,9 +511,13 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
- error_setg(errp, "Zve32f/Zve64f extensions require F extension");
- return;
+ /* The Zve32f extension depends on the Zve32x extension */
+ if (cpu->cfg.ext_zve32f) {
+ if (!riscv_has_ext(env, RVF)) {
+ error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+ return;
+ }
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
}
if (cpu->cfg.ext_zvfh) {
@@ -658,13 +662,9 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
}
- /*
- * In principle Zve*x would also suffice here, were they supported
- * in qemu
- */
if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
- cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
+ cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
error_setg(errp,
"Vector crypto extensions require V or Zve* extensions");
return;
--
2.43.2
next prev parent reply other threads:[~2024-03-25 8:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-25 8:33 [PATCH v2 0/5] target/riscv: Support Zve32x and Zve64x extensions Jason Chien
2024-03-25 8:33 ` Jason Chien [this message]
2024-03-27 17:35 ` [PATCH v2 1/5] target/riscv: Add support for Zve32x extension Daniel Henrique Barboza
2024-03-25 8:33 ` [PATCH v2 2/5] target/riscv: Expose Zve32x extension to users Jason Chien
2024-03-27 17:37 ` Daniel Henrique Barboza
2024-03-25 8:33 ` [PATCH v2 3/5] target/riscv: Add support for Zve64x extension Jason Chien
2024-03-27 18:02 ` Daniel Henrique Barboza
2024-03-25 8:33 ` [PATCH v2 4/5] target/riscv: Expose Zve64x extension to users Jason Chien
2024-03-25 8:33 ` [PATCH v2 5/5] target/riscv: Relax vector register check in RISCV gdbstub Jason Chien
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