From: Himanshu Chauhan <hchauhan@ventanamicro.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH v4 3/3] target/riscv: Enable sdtrig for Ventana's Veyron CPUs
Date: Wed, 13 Mar 2024 11:39:31 +0530 [thread overview]
Message-ID: <20240313060931.242161-4-hchauhan@ventanamicro.com> (raw)
In-Reply-To: <20240313060931.242161-1-hchauhan@ventanamicro.com>
Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable
the sdtrig extension and disable the debug property for these CPUs.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ab057a0926..9ddebe468b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -568,7 +568,9 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
cpu->cfg.ext_zicbom = true;
cpu->cfg.cbom_blocksize = 64;
cpu->cfg.cboz_blocksize = 64;
+ cpu->cfg.debug=false;
cpu->cfg.ext_zicboz = true;
+ cpu->cfg.ext_sdtrig = true;
cpu->cfg.ext_smaia = true;
cpu->cfg.ext_ssaia = true;
cpu->cfg.ext_sscofpmf = true;
--
2.34.1
next prev parent reply other threads:[~2024-03-13 6:11 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-13 6:09 [PATCH v4 0/3] Introduce sdtrig ISA extension Himanshu Chauhan
2024-03-13 6:09 ` [PATCH v4 1/3] target/riscv: Enable mcontrol6 triggers only when sdtrig is selected Himanshu Chauhan
2024-03-13 9:52 ` Andrew Jones
2024-03-13 6:09 ` [PATCH v4 2/3] target/riscv: Expose sdtrig ISA extension Himanshu Chauhan
2024-03-13 9:54 ` Andrew Jones
2024-03-13 10:20 ` Himanshu Chauhan
2024-03-13 10:58 ` Andrew Jones
2024-03-13 12:18 ` Himanshu Chauhan
2024-03-13 12:49 ` Andrew Jones
2024-03-13 13:31 ` Himanshu Chauhan
2024-03-13 6:09 ` Himanshu Chauhan [this message]
2024-03-13 9:55 ` [PATCH v4 3/3] target/riscv: Enable sdtrig for Ventana's Veyron CPUs Andrew Jones
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