From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
qemu-riscv@nongnu.org (open list:RISC-V TCG target)
Subject: [PULL 29/29] target/riscv: honour show_opcodes when disassembling
Date: Wed, 6 Mar 2024 14:40:41 +0000 [thread overview]
Message-ID: <20240306144041.3787188-30-alex.bennee@linaro.org> (raw)
In-Reply-To: <20240306144041.3787188-1-alex.bennee@linaro.org>
This makes the output suitable when used for plugins.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240305121005.3528075-30-alex.bennee@linaro.org>
diff --git a/disas/riscv.c b/disas/riscv.c
index 8a546d5ea53..e236c8b5b7c 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -5192,19 +5192,21 @@ print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
}
}
- switch (len) {
- case 2:
- (*info->fprintf_func)(info->stream, INST_FMT_2, inst);
- break;
- case 4:
- (*info->fprintf_func)(info->stream, INST_FMT_4, inst);
- break;
- case 6:
- (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
- break;
- default:
- (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
- break;
+ if (info->show_opcodes) {
+ switch (len) {
+ case 2:
+ (*info->fprintf_func)(info->stream, INST_FMT_2, inst);
+ break;
+ case 4:
+ (*info->fprintf_func)(info->stream, INST_FMT_4, inst);
+ break;
+ case 6:
+ (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
+ break;
+ default:
+ (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
+ break;
+ }
}
disasm_inst(buf, sizeof(buf), isa, memaddr, inst,
--
2.39.2
parent reply other threads:[~2024-03-06 14:49 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <20240306144041.3787188-1-alex.bennee@linaro.org>]
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