From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
Andrew Jones <ajones@ventanamicro.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v4 4/6] target/riscv: Reset henvcfg to zero
Date: Thu, 15 Feb 2024 19:39:53 -0300 [thread overview]
Message-ID: <20240215223955.969568-5-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20240215223955.969568-1-dbarboza@ventanamicro.com>
From: Andrew Jones <ajones@ventanamicro.com>
The hypervisor should decide what it wants to enable. Zero all
configuration enable bits on reset.
Also, commit ed67d63798f2 ("target/riscv: Update CSR bits name for
svadu extension") missed one reference to 'hade'. Change it now.
Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address translation")
Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 3 +--
target/riscv/csr.c | 2 +-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f424751962..e5eef3a4de 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -961,8 +961,7 @@ static void riscv_cpu_reset_hold(Object *obj)
env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
(cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
- env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
- (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0);
+ env->henvcfg = 0;
/* Initialized default priorities of local interrupts. */
for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d4e8ac13b9..cc9cef3d85 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2133,7 +2133,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
/*
* henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
* henvcfg.stce is read_only 0 when menvcfg.stce = 0
- * henvcfg.hade is read_only 0 when menvcfg.hade = 0
+ * henvcfg.adue is read_only 0 when menvcfg.adue = 0
*/
*val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) |
env->menvcfg);
--
2.43.0
next prev parent reply other threads:[~2024-02-15 22:40 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-15 22:39 [PATCH v4 0/6] riscv: named features riscv,isa, 'svade' rework Daniel Henrique Barboza
2024-02-15 22:39 ` [PATCH v4 1/6] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile() Daniel Henrique Barboza
2024-02-15 22:39 ` [PATCH v4 2/6] target/riscv: add riscv,isa to named features Daniel Henrique Barboza
2024-02-15 22:39 ` [PATCH v4 3/6] target/riscv: add remaining " Daniel Henrique Barboza
2024-02-15 22:39 ` Daniel Henrique Barboza [this message]
2024-02-15 22:39 ` [PATCH v4 5/6] target/riscv: Gate hardware A/D PTE bit updating Daniel Henrique Barboza
2024-02-15 22:39 ` [PATCH v4 6/6] target/riscv: Promote svade to a normal extension Daniel Henrique Barboza
2024-02-15 23:49 ` [PATCH v4 0/6] riscv: named features riscv,isa, 'svade' rework Alistair Francis
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