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From: Himanshu Chauhan <hchauhan@ventanamicro.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH 1/2] target/riscv: Export sdtrig as an extension and ISA string
Date: Wed, 10 Jan 2024 09:32:02 +0530	[thread overview]
Message-ID: <20240110040203.1920924-2-hchauhan@ventanamicro.com> (raw)
In-Reply-To: <20240110040203.1920924-1-hchauhan@ventanamicro.com>

This patch makes the debug trigger (sdtrig) capability
as an extension and exports it as an ISA string. The sdtrig
extension may or may not be implemented in a system. The
	-cpu rv64,sdtrig=<true/false>
option can be used to dynamicaly turn sdtrig extension
on or off.

Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
---
 target/riscv/cpu.c     | 2 ++
 target/riscv/cpu_cfg.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b07a76ef6b..aaa2d4ff1d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -143,6 +143,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
+    ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig),
     ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
     ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
     ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
@@ -1306,6 +1307,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
     MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
 
+    MULTI_EXT_CFG_BOOL("sdtrig", ext_sdtrig, true),
     MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
     MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
     MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index f4605fb190..3d3acc7f90 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -113,6 +113,7 @@ struct RISCVCPUConfig {
     bool ext_ssaia;
     bool ext_sscofpmf;
     bool ext_smepmp;
+    bool ext_sdtrig;
     bool rvv_ta_all_1s;
     bool rvv_ma_all_1s;
 
-- 
2.34.1



  reply	other threads:[~2024-01-10  4:02 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-10  4:02 [PATCH 0/2] Export debug triggers as an extension Himanshu Chauhan
2024-01-10  4:02 ` Himanshu Chauhan [this message]
2024-01-12  3:34   ` [PATCH 1/2] target/riscv: Export sdtrig as an extension and ISA string Alistair Francis
2024-01-10  4:02 ` [PATCH 2/2] target/riscv: Raise an exception when sdtrig is turned off Himanshu Chauhan
2024-01-12  3:33   ` Alistair Francis
2024-01-10 19:19 ` [PATCH 0/2] Export debug triggers as an extension Daniel Henrique Barboza
2024-01-12  3:52   ` Alistair Francis
2024-01-12 13:34     ` Rob Bradford
2024-01-17 16:59       ` Daniel Henrique Barboza
2024-01-17 17:44         ` Himanshu Chauhan
2024-01-22  5:42       ` Alistair Francis
2024-01-22  9:16         ` Andrew Jones
2024-02-05  4:05           ` Alistair Francis
2024-02-05  4:50             ` Anup Patel
2024-02-05  5:57               ` Alistair Francis

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