From: Atish Patra <atishp@rivosinc.com>
Cc: Kaiwen Xue <kaiwenx@rivosinc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Atish Patra <atishp@rivosinc.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Weiwei Li <liwei1518@gmail.com>,
kaiwenxue1@gmail.com
Subject: [PATCH v4 3/5] target/riscv: Add cycle & instret privilege mode filtering definitions
Date: Mon, 8 Jan 2024 16:25:52 -0800 [thread overview]
Message-ID: <20240109002554.646572-4-atishp@rivosinc.com> (raw)
In-Reply-To: <20240109002554.646572-1-atishp@rivosinc.com>
From: Kaiwen Xue <kaiwenx@rivosinc.com>
This adds the definitions for ISA extension smcntrpmf.
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/cpu.h | 6 ++++++
target/riscv/cpu_bits.h | 29 +++++++++++++++++++++++++++++
2 files changed, 35 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d74b361be641..34617c4c4bab 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -319,6 +319,12 @@ struct CPUArchState {
target_ulong mcountinhibit;
+ /* PMU cycle & instret privilege mode filtering */
+ target_ulong mcyclecfg;
+ target_ulong mcyclecfgh;
+ target_ulong minstretcfg;
+ target_ulong minstretcfgh;
+
/* PMU counter state */
PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index ebd7917d490a..0ee91e502e8f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -401,6 +401,10 @@
/* Machine counter-inhibit register */
#define CSR_MCOUNTINHIBIT 0x320
+/* Machine counter configuration registers */
+#define CSR_MCYCLECFG 0x321
+#define CSR_MINSTRETCFG 0x322
+
#define CSR_MHPMEVENT3 0x323
#define CSR_MHPMEVENT4 0x324
#define CSR_MHPMEVENT5 0x325
@@ -431,6 +435,9 @@
#define CSR_MHPMEVENT30 0x33e
#define CSR_MHPMEVENT31 0x33f
+#define CSR_MCYCLECFGH 0x721
+#define CSR_MINSTRETCFGH 0x722
+
#define CSR_MHPMEVENT3H 0x723
#define CSR_MHPMEVENT4H 0x724
#define CSR_MHPMEVENT5H 0x725
@@ -885,6 +892,28 @@ typedef enum RISCVException {
/* PMU related bits */
#define MIE_LCOFIE (1 << IRQ_PMU_OVF)
+#define MCYCLECFG_BIT_MINH BIT_ULL(62)
+#define MCYCLECFGH_BIT_MINH BIT(30)
+#define MCYCLECFG_BIT_SINH BIT_ULL(61)
+#define MCYCLECFGH_BIT_SINH BIT(29)
+#define MCYCLECFG_BIT_UINH BIT_ULL(60)
+#define MCYCLECFGH_BIT_UINH BIT(28)
+#define MCYCLECFG_BIT_VSINH BIT_ULL(59)
+#define MCYCLECFGH_BIT_VSINH BIT(27)
+#define MCYCLECFG_BIT_VUINH BIT_ULL(58)
+#define MCYCLECFGH_BIT_VUINH BIT(26)
+
+#define MINSTRETCFG_BIT_MINH BIT_ULL(62)
+#define MINSTRETCFGH_BIT_MINH BIT(30)
+#define MINSTRETCFG_BIT_SINH BIT_ULL(61)
+#define MINSTRETCFGH_BIT_SINH BIT(29)
+#define MINSTRETCFG_BIT_UINH BIT_ULL(60)
+#define MINSTRETCFGH_BIT_UINH BIT(28)
+#define MINSTRETCFG_BIT_VSINH BIT_ULL(59)
+#define MINSTRETCFGH_BIT_VSINH BIT(27)
+#define MINSTRETCFG_BIT_VUINH BIT_ULL(58)
+#define MINSTRETCFGH_BIT_VUINH BIT(26)
+
#define MHPMEVENT_BIT_OF BIT_ULL(63)
#define MHPMEVENTH_BIT_OF BIT(31)
#define MHPMEVENT_BIT_MINH BIT_ULL(62)
--
2.34.1
next prev parent reply other threads:[~2024-01-09 0:27 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-09 0:25 [PATCH v4 0/5] Add ISA extension smcntrpmf support Atish Patra
2024-01-09 0:25 ` [PATCH v4 1/5] target/riscv: Fix the predicate functions for mhpmeventhX CSRs Atish Patra
2024-01-09 0:25 ` [PATCH v4 2/5] target/riscv: Add cycle & instret privilege mode filtering properties Atish Patra
2024-01-09 18:37 ` Daniel Henrique Barboza
2024-01-22 4:55 ` Alistair Francis
2024-01-09 0:25 ` Atish Patra [this message]
2024-01-22 4:56 ` [PATCH v4 3/5] target/riscv: Add cycle & instret privilege mode filtering definitions Alistair Francis
2024-01-09 0:25 ` [PATCH v4 4/5] target/riscv: Add cycle & instret privilege mode filtering support Atish Patra
2024-01-22 4:58 ` Alistair Francis
2024-01-09 0:25 ` [PATCH v4 5/5] target/riscv: Implement privilege mode filtering for cycle/instret Atish Patra
2024-01-22 5:04 ` Alistair Francis
2024-01-24 0:15 ` Atish Kumar Patra
2024-02-05 19:38 ` Atish Kumar Patra
2024-02-15 4:45 ` Alistair Francis
2024-02-15 4:45 ` Alistair Francis
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