From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
bin.meng@windriver.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v3 25/37] target/riscv: Non-SIMD Q31 saturation ALU Instructions
Date: Thu, 24 Jun 2021 18:55:09 +0800 [thread overview]
Message-ID: <20210624105521.3964-26-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com>
Q31 saturation is to limit the result to the range
[INT32_MIN, INT32_MAX].
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 15 ++
target/riscv/insn32.decode | 16 ++
target/riscv/insn_trans/trans_rvp.c.inc | 17 ++
target/riscv/packed_helper.c | 214 ++++++++++++++++++++++++
4 files changed, 262 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 6ce22a186e..b3485f95a2 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1369,3 +1369,18 @@ DEF_HELPER_3(khmbt, tl, env, tl, tl)
DEF_HELPER_3(khmtt, tl, env, tl, tl)
DEF_HELPER_3(ukaddh, tl, env, tl, tl)
DEF_HELPER_3(uksubh, tl, env, tl, tl)
+
+DEF_HELPER_3(kaddw, tl, env, tl, tl)
+DEF_HELPER_3(ukaddw, tl, env, tl, tl)
+DEF_HELPER_3(ksubw, tl, env, tl, tl)
+DEF_HELPER_3(uksubw, tl, env, tl, tl)
+DEF_HELPER_3(kdmbb, tl, env, tl, tl)
+DEF_HELPER_3(kdmbt, tl, env, tl, tl)
+DEF_HELPER_3(kdmtt, tl, env, tl, tl)
+DEF_HELPER_3(kslraw, tl, env, tl, tl)
+DEF_HELPER_3(kslraw_u, tl, env, tl, tl)
+DEF_HELPER_3(ksllw, tl, env, tl, tl)
+DEF_HELPER_4(kdmabb, tl, env, tl, tl, tl)
+DEF_HELPER_4(kdmabt, tl, env, tl, tl, tl)
+DEF_HELPER_4(kdmatt, tl, env, tl, tl, tl)
+DEF_HELPER_2(kabsw, tl, env, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f465851f03..a25294baab 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -972,3 +972,19 @@ khmbt 0001110 ..... ..... 001 ..... 1110111 @r
khmtt 0010110 ..... ..... 001 ..... 1110111 @r
ukaddh 0001010 ..... ..... 001 ..... 1110111 @r
uksubh 0001011 ..... ..... 001 ..... 1110111 @r
+
+kaddw 0000000 ..... ..... 001 ..... 1110111 @r
+ukaddw 0001000 ..... ..... 001 ..... 1110111 @r
+ksubw 0000001 ..... ..... 001 ..... 1110111 @r
+uksubw 0001001 ..... ..... 001 ..... 1110111 @r
+kdmbb 0000101 ..... ..... 001 ..... 1110111 @r
+kdmbt 0001101 ..... ..... 001 ..... 1110111 @r
+kdmtt 0010101 ..... ..... 001 ..... 1110111 @r
+kslraw 0110111 ..... ..... 001 ..... 1110111 @r
+kslraw_u 0111111 ..... ..... 001 ..... 1110111 @r
+ksllw 0010011 ..... ..... 001 ..... 1110111 @r
+kslliw 0011011 ..... ..... 001 ..... 1110111 @sh5
+kdmabb 1101001 ..... ..... 001 ..... 1110111 @r
+kdmabt 1110001 ..... ..... 001 ..... 1110111 @r
+kdmatt 1111001 ..... ..... 001 ..... 1110111 @r
+kabsw 1010110 10100 ..... 000 ..... 1110111 @r2
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index 48eb190bc6..d2c7ab1440 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -681,3 +681,20 @@ GEN_RVP_R_OOL(khmbt);
GEN_RVP_R_OOL(khmtt);
GEN_RVP_R_OOL(ukaddh);
GEN_RVP_R_OOL(uksubh);
+
+/* Non-SIMD Q31 saturation ALU Instructions */
+GEN_RVP_R_OOL(kaddw);
+GEN_RVP_R_OOL(ukaddw);
+GEN_RVP_R_OOL(ksubw);
+GEN_RVP_R_OOL(uksubw);
+GEN_RVP_R_OOL(kdmbb);
+GEN_RVP_R_OOL(kdmbt);
+GEN_RVP_R_OOL(kdmtt);
+GEN_RVP_R_OOL(kslraw);
+GEN_RVP_R_OOL(kslraw_u);
+GEN_RVP_R_OOL(ksllw);
+GEN_RVP_SHIFTI(kslliw, NULL, gen_helper_ksllw);
+GEN_RVP_R_ACC_OOL(kdmabb);
+GEN_RVP_R_ACC_OOL(kdmabt);
+GEN_RVP_R_ACC_OOL(kdmatt);
+GEN_RVP_R2_OOL(kabsw);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 171f88face..89d203730d 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -2604,3 +2604,217 @@ static inline void do_uksubh(CPURISCVState *env, void *vd, void *va,
}
RVPR(uksubh, 2, 4);
+
+/* Q31 saturation Instructions */
+static inline void do_kaddw(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int32_t *a = va, *b = vb;
+
+ *d = sadd32(env, 0, a[H4(i)], b[H4(i)]);
+}
+
+RVPR(kaddw, 2, 4);
+
+static inline void do_ukaddw(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ uint32_t *a = va, *b = vb;
+
+ *d = (int32_t)saddu32(env, 0, a[H4(i)], b[H4(i)]);
+}
+
+RVPR(ukaddw, 2, 4);
+
+static inline void do_ksubw(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int32_t *a = va, *b = vb;
+
+ *d = ssub32(env, 0, a[H4(i)], b[H4(i)]);
+}
+
+RVPR(ksubw, 2, 4);
+
+static inline void do_uksubw(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ uint32_t *a = va, *b = vb;
+
+ *d = (int32_t)ssubu32(env, 0, a[H4(i)], b[H4(i)]);
+}
+
+RVPR(uksubw, 2, 4);
+
+static inline void do_kdmbb(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int16_t *a = va, *b = vb;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i)] == INT16_MIN) {
+ *d = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ *d = (int64_t)a[H2(i)] * b[H2(i)] << 1;
+ }
+}
+
+RVPR(kdmbb, 4, 2);
+
+static inline void do_kdmbt(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int16_t *a = va, *b = vb;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ *d = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ *d = (int64_t)a[H2(i)] * b[H2(i + 1)] << 1;
+ }
+}
+
+RVPR(kdmbt, 4, 2);
+
+static inline void do_kdmtt(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int16_t *a = va, *b = vb;
+
+ if (a[H2(i + 1)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ *d = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ *d = (int64_t)a[H2(i + 1)] * b[H2(i + 1)] << 1;
+ }
+}
+
+RVPR(kdmtt, 4, 2);
+
+static inline void do_kslraw(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int32_t *a = va;
+ int32_t shift = sextract32((*(uint32_t *)vb), 0, 6);
+
+ if (shift >= 0) {
+ *d = (int32_t)sat64(env, (int64_t)a[H4(i)] << shift, 31);
+ } else {
+ shift = -shift;
+ shift = (shift == 32) ? 31 : shift;
+ *d = a[H4(i)] >> shift;
+ }
+}
+
+RVPR(kslraw, 2, 4);
+
+static inline void do_kslraw_u(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int32_t *a = va;
+ int32_t shift = sextract32((*(uint32_t *)vb), 0, 6);
+
+ if (shift >= 0) {
+ *d = (int32_t)sat64(env, (int64_t)a[H4(i)] << shift, 31);
+ } else {
+ shift = -shift;
+ shift = (shift == 32) ? 31 : shift;
+ *d = vssra32(env, 0, a[H4(i)], shift);
+ }
+}
+
+RVPR(kslraw_u, 2, 4);
+
+static inline void do_ksllw(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int32_t *a = va;
+ uint8_t shift = *(uint8_t *)vb & 0x1f;
+
+ *d = (int32_t)sat64(env, (int64_t)a[H4(i)] << shift, 31);
+}
+
+RVPR(ksllw, 2, 4);
+
+static inline void do_kdmabb(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+
+{
+ target_long *d = vd;
+ int16_t *a = va, *b = vb;
+ int32_t *c = vc, m0;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i)] == INT16_MIN) {
+ m0 = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ m0 = (int32_t)a[H2(i)] * b[H2(i)] << 1;
+ }
+ *d = sadd32(env, 0, c[H4(i)], m0);
+}
+
+RVPR_ACC(kdmabb, 4, 2);
+
+static inline void do_kdmabt(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+
+{
+ target_long *d = vd;
+ int16_t *a = va, *b = vb;
+ int32_t *c = vc, m0;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ m0 = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ m0 = (int32_t)a[H2(i)] * b[H2(i + 1)] << 1;
+ }
+ *d = sadd32(env, 0, c[H4(i)], m0);
+}
+
+RVPR_ACC(kdmabt, 4, 2);
+
+static inline void do_kdmatt(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+
+{
+ target_long *d = vd;
+ int16_t *a = va, *b = vb;
+ int32_t *c = vc, m0;
+
+ if (a[H2(i + 1)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ m0 = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ m0 = (int32_t)a[H2(i + 1)] * b[H2(i + 1)] << 1;
+ }
+ *d = sadd32(env, 0, c[H4(i)], m0);
+}
+
+RVPR_ACC(kdmatt, 4, 2);
+
+static inline void do_kabsw(CPURISCVState *env, void *vd, void *va, uint8_t i)
+
+{
+ target_long *d = vd;
+ int32_t *a = va;
+
+ if (a[H4(i)] == INT32_MIN) {
+ *d = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ *d = (int32_t)abs(a[H4(i)]);
+ }
+}
+
+RVPR2(kabsw, 2, 4);
--
2.17.1
next prev parent reply other threads:[~2021-06-24 11:09 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-24 10:54 [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-07-01 2:02 ` Alistair Francis
2021-06-24 10:54 ` [PATCH v3 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-07-01 2:08 ` Alistair Francis
2021-06-24 10:54 ` [PATCH v3 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-06-24 10:55 ` LIU Zhiwei [this message]
2021-06-24 10:55 ` [PATCH v3 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-06-24 11:55 ` [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 no-reply
2021-07-01 1:30 ` Alistair Francis
2021-07-01 3:06 ` LIU Zhiwei
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