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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
	bmeng@tinylab.org, liwei1518@gmail.com,
	zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
	philmd@linaro.org
Subject: Re: [PATCH for-9.0 v13 4/8] target/riscv: always clear vstart in whole vec move insns
Date: Wed, 13 Mar 2024 18:39:22 -0300	[thread overview]
Message-ID: <1fc1db23-6942-4968-8978-40999c50936c@ventanamicro.com> (raw)
In-Reply-To: <87936b8f-4900-4a5f-a63d-266c1550c9a1@linaro.org>



On 3/13/24 18:16, Richard Henderson wrote:
> On 3/13/24 09:30, Daniel Henrique Barboza wrote:
>> These insns have 2 paths: we'll either have vstart already cleared if
>> vstart_eq_zero or we'll do a brcond to check if vstart >= maxsz to call
>> the 'vmvr_v' helper. The helper will clear vstart if it executes until
>> the end, or if vstart >= vl.
>>
>> However, if vstart >= maxsz, the helper will be skipped, and vstart
>> won't be cleared since the helper is being responsible from doing it.
>>
>> We want to make the helpers responsible to manage vstart, including
>> these corner cases, precisely to avoid these situations. Move the vstart
>>> = maxsz cond to the helper, and be sure to clear vstart if that
>> happens.  This way we're now 100% sure that vstart is being clearer in
>> the end of the execution, regardless of the path taken.
>>
>> Fixes: f714361ed7 ("target/riscv: rvv-1.0: implement vstart CSR")
>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>>   target/riscv/insn_trans/trans_rvv.c.inc | 3 ---
>>   target/riscv/vector_helper.c            | 5 +++++
>>   2 files changed, 5 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
>> index 8c16a9f5b3..52c26a7834 100644
>> --- a/target/riscv/insn_trans/trans_rvv.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
>> @@ -3664,12 +3664,9 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a)               \
>>                                vreg_ofs(s, a->rs2), maxsz, maxsz);        \
>>               mark_vs_dirty(s);                                           \
>>           } else {                                                        \
>> -            TCGLabel *over = gen_new_label();                           \
>> -            tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over);  \
>>               tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
>>                                  tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
>>               mark_vs_dirty(s);                                           \
>> -            gen_set_label(over);                                        \
>>           }                                                               \
>>           return true;                                                    \
>>       }                                                                   \
>> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
>> index b4360dbd52..7260a5972b 100644
>> --- a/target/riscv/vector_helper.c
>> +++ b/target/riscv/vector_helper.c
>> @@ -5163,6 +5163,11 @@ void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
>>       VSTART_CHECK_EARLY_EXIT(env);
>> +    if (env->vstart >= maxsz) {
>> +        env->vstart = 0;
>> +        return;
>> +    }
> 
> Did you need the VSTART_CHECK_EARLY_EXIT here then?
> It certainly seems like the vstart >= vl check is redundant...

Hmm right. I thought about maxsz being calculated via vlmax, and vlmax not necessarily
being == vl ... but vlmax will be always >= vl. So the vstart >= vl check s supersed
by vstart >= maxsz.


I'll re-send. Thanks,

Daniel

> 
> 
> r~


  reply	other threads:[~2024-03-13 21:39 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-13 19:30 [PATCH for-9.0 v13 0/8] riscv: set vstart_eq_zero on vector insns Daniel Henrique Barboza
2024-03-13 19:30 ` [PATCH for-9.0 v13 1/8] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX() Daniel Henrique Barboza
2024-03-13 19:30 ` [PATCH for-9.0 v13 2/8] trans_rvv.c.inc: set vstart = 0 in int scalar move insns Daniel Henrique Barboza
2024-03-13 19:30 ` [PATCH for-9.0 v13 3/8] target/riscv/vector_helpers: do early exit when vstart >= vl Daniel Henrique Barboza
2024-03-13 19:30 ` [PATCH for-9.0 v13 4/8] target/riscv: always clear vstart in whole vec move insns Daniel Henrique Barboza
2024-03-13 21:16   ` Richard Henderson
2024-03-13 21:39     ` Daniel Henrique Barboza [this message]
2024-03-13 19:30 ` [PATCH for-9.0 v13 5/8] target/riscv: remove 'over' brconds from vector trans Daniel Henrique Barboza
2024-03-13 19:30 ` [PATCH for-9.0 v13 6/8] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls Daniel Henrique Barboza
2024-03-13 19:30 ` [PATCH for-9.0 v13 7/8] target/riscv: enable 'vstart_eq_zero' in the end of insns Daniel Henrique Barboza
2024-03-13 19:30 ` [PATCH for-9.0 v13 8/8] target/riscv/vector_helper.c: optimize loops in ldst helpers Daniel Henrique Barboza

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