[PATCH v3] hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs
2024-06-12 12:50 UTC (3+ messages)
[PATCH v3 00/13] riscv: QEMU RISC-V IOMMU Support
2024-06-12 12:10 UTC (26+ messages)
` [PATCH v3 02/13] hw/riscv: add riscv-iommu-bits.h
` [PATCH v3 03/13] hw/riscv: add RISC-V IOMMU base emulation
` [PATCH v3 05/13] hw/riscv: add riscv-iommu-pci reference device
` [PATCH v3 08/13] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
` [PATCH v3 10/13] hw/riscv/riscv-iommu: add ATS support
` [PATCH v3 11/13] hw/riscv/riscv-iommu: add DBG support
[RFC PATCH 00/16] Implements RISC-V WorldGuard extension v0.4
2024-06-12 8:14 UTC (17+ messages)
` [RFC PATCH 01/16] accel/tcg: Store section pointer in CPUTLBEntryFull
` [RFC PATCH 02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU
` [RFC PATCH 03/16] exec: Add RISC-V WorldGuard WID to MemTxAttrs
` [RFC PATCH 04/16] hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config
` [RFC PATCH 05/16] target/riscv: Add CPU options of WorldGuard CPU extension
` [RFC PATCH 06/16] target/riscv: Add hard-coded CPU state of WG extension
` [RFC PATCH 07/16] target/riscv: Add defines for WorldGuard CSRs
` [RFC PATCH 08/16] target/riscv: Allow global WG config to set WG CPU callbacks
` [RFC PATCH 09/16] target/riscv: Implement WorldGuard CSRs
` [RFC PATCH 10/16] target/riscv: Add WID to MemTxAttrs of CPU memory transactions
` [RFC PATCH 11/16] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU
` [RFC PATCH 12/16] hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker
` [RFC PATCH 13/16] hw/misc: riscv_wgchecker: Implement wgchecker slot registers
` [RFC PATCH 14/16] hw/misc: riscv_wgchecker: Implement correct block-access behavior
` [RFC PATCH 15/16] hw/misc: riscv_wgchecker: Check the slot settings in translate
` [RFC PATCH 16/16] hw/riscv: virt: Add WorldGuard support
[PATCH v7 0/2] Support RISC-V IOPMP
2024-06-12 3:17 UTC (3+ messages)
` [PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device
` [PATCH v7 2/2] hw/riscv/virt: Add IOPMP support
[PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext
2024-06-12 3:13 UTC (21+ messages)
` [PATCH 1/6] target/riscv: Remove obsolete sfence.vm instruction
` [PATCH 3/6] target/riscv: Add support for Control Transfer Records extension CSRs
` [PATCH 4/6] target/riscv: Add support to record CTR entries
` [PATCH 5/6] target/riscv: Add CTR sctrclr instruction
` [PATCH 6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs
qemu-riscv32 usermode still broken?
2024-06-12 1:26 UTC (7+ messages)
[PATCH RESEND 0/6] Introduce extension implied rules
2024-06-12 1:21 UTC (13+ messages)
` [PATCH RESEND 1/6] target/riscv: Introduce extension implied rules definition
` [PATCH RESEND 2/6] target/riscv: Introduce extension implied rule helpers
` [PATCH RESEND 3/6] target/riscv: Add MISA implied rules
` [PATCH RESEND 4/6] target/riscv: Add standard extension "
` [PATCH RESEND 5/6] target/riscv: Add Zc extension implied rule
` [PATCH RESEND 6/6] target/riscv: Remove extension auto-update check statements
[PATCH v3 0/5] semihosting: Restrict to TCG
2024-06-11 10:07 UTC (9+ messages)
` [PATCH v3 1/5] target/m68k: Restrict semihosting "
` [PATCH v3 2/5] target/xtensa: "
` [PATCH v3 3/5] target/mips: "
` [PATCH v3 4/5] target/riscv: "
` [PATCH v3 5/5] semihosting: Restrict "
[PATCH] target/riscv: Fix froundnx.h nanbox check
2024-06-08 21:45 UTC
[PATCH] target/riscv: support atomic instruction fetch (Ziccif)
2024-06-07 13:39 UTC (2+ messages)
[PATCH v4 0/6] target/riscv: Support RISC-V privilege 1.13 spec
2024-06-07 5:04 UTC (9+ messages)
` [PATCH v4 1/6] target/riscv: Reuse the conversion function of priv_spec
` [PATCH v4 2/6] target/riscv: Define macros and variables for ss1p13
` [PATCH v4 3/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0
` [PATCH v4 4/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
` [PATCH v4 5/6] target/riscv: Reserve exception codes for sw-check and hw-err
` [PATCH v4 6/6] target/riscv: Support the version for ss1p13
[PATCH v3 0/6] target/riscv: Support RISC-V privilege 1.13 spec
2024-06-06 13:43 UTC (11+ messages)
` [PATCH v3 1/6] target/riscv: Reuse the conversion function of priv_spec
` [PATCH v3 2/6] target/riscv: Define macros and variables for ss1p13
` [PATCH v3 3/6] target/riscv: Support the version "
` [PATCH v3 4/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0
` [PATCH v3 5/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
` [PATCH v3 6/6] target/riscv: Reserve exception codes for sw-check and hw-err
[PATCH 0/3] RISC-V: ACPI: Namespace updates
2024-06-06 9:49 UTC (11+ messages)
` [PATCH 1/3] gpex-acpi: Support PCI link devices outside the host bridge
` [PATCH 2/3] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
` [PATCH 3/3] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
[PATCH v4 0/3] target/riscv/kvm: QEMU support for KVM Guest Debug on RISC-V
2024-06-06 1:56 UTC (5+ messages)
` [PATCH v4 1/3] target/riscv/kvm: add software breakpoints support
` [PATCH v4 2/3] target/riscv/kvm: handle the exit with debug reason
` [PATCH v4 3/3] target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG
[PATCH v3 0/3] target/riscv/kvm: QEMU support for KVM Guest Debug on RISC-V
2024-06-05 23:51 UTC (5+ messages)
` [PATCH v3 1/3] target/riscv/kvm: add software breakpoints support
` [PATCH v3 2/3] target/riscv/kvm: handle the exit with debug reason
` [PATCH v3 3/3] target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG
[PATCH RFC 0/8] Add Counter delegation ISA extension support
2024-06-05 11:49 UTC (5+ messages)
` [PATCH RFC 2/8] target/riscv: Decouple AIA processing from xiselect and xireg
` [PATCH RFC 4/8] target/riscv: Support generic CSR indirect access
[PATCH 0/6] Introduce extension implied rules
2024-06-05 6:54 UTC (4+ messages)
` [PATCH 2/6] target/riscv: Introduce extension implied rule helpers
[PATCH v2 0/8] hw/riscv/virt.c: aplic/imsic DT fixes
2024-06-05 0:43 UTC (19+ messages)
` [PATCH v2 1/8] hw/riscv/virt.c: add address-cells in create_fdt_one_aplic()
` [PATCH v2 2/8] hw/riscv/virt.c: add aplic nodename helper
` [PATCH v2 3/8] hw/riscv/virt.c: rename aplic nodename to 'interrupt-controller'
` [PATCH v2 4/8] hw/riscv/virt.c: aplic DT: add 'qemu, aplic' to 'compatible'
` [PATCH v2 5/8] hw/riscv/virt.c: aplic DT: rename prop to 'riscv, delegation'
` [PATCH v2 6/8] hw/riscv/virt.c: change imsic nodename to 'interrupt-controller'
` [PATCH v2 7/8] hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible'
` [PATCH v2 8/8] hw/riscv/virt.c: imsics DT: add '#msi-cells'
[PATCH RESEND v2 0/3] target/riscv/kvm: QEMU support for KVM Guest Debug on RISC-V
2024-06-04 23:13 UTC (7+ messages)
` [PATCH RESEND v2 1/3] target/riscv/kvm: add software breakpoints support
` [PATCH RESEND v2 2/3] target/riscv/kvm: handle the exit with debug reason
` [PATCH RESEND v2 3/3] target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG
[RFC v2 0/7] Introduce SMP Cache Topology
2024-06-04 16:08 UTC (15+ messages)
` [RFC v2 1/7] hw/core: Make CPU topology enumeration arch-agnostic
` [RFC v2 3/7] hw/core: Add cache topology options in -smp
[PATCH] target/riscv: rvzicbo: Fixup CBO extension register calculation
2024-06-04 11:37 UTC (5+ messages)
[PATCH v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
2024-06-04 9:04 UTC
[PATCH] target/riscv: Use get_address() to get address with Zicbom extensions
2024-06-04 8:08 UTC (4+ messages)
[PATCH v2 00/12] Add support for RISC-V ACPI tests
2024-06-04 7:04 UTC (11+ messages)
` [PATCH v2 01/12] uefi-test-tools/UefiTestToolsPkg: Add RISC-V support
` [PATCH v2 10/12] tests/qtest/bios-tables-test: Add empty ACPI data files for RISC-V
` [PATCH v2 11/12] tests/qtest/bios-tables-test.c: Enable basic testing "
` [PATCH v2 12/12] tests/qtest/bios-tables-test: Add expected ACPI data files "
[PATCH 0/4] hw/dma: Add error handling for loading descriptions failing
2024-06-04 7:01 UTC (15+ messages)
` [PATCH 1/4] hw/dma: Enhance error handling in loading description
` [PATCH 2/4] hw/dma: Break the loop when loading descriptions fails
` [PATCH 3/4] hw/dma: Add a trace log for a description loading failure
` [PATCH 4/4] hw/net: Fix the transmission return size
[PATCH v5 0/4] RISC-V: Modularize common match conditions for trigger
2024-06-04 6:42 UTC (6+ messages)
` [PATCH v5 1/4] target/riscv: Add functions for common matching conditions of trigger
` [PATCH v5 2/4] target/riscv: Apply modularized matching conditions for breakpoint
` [PATCH v5 3/4] target/riscv: Apply modularized matching conditions for watchpoint
` [PATCH v5 4/4] target/riscv: Apply modularized matching conditions for icount trigger
[PATCH v4 0/4] RISC-V: Modularize common match conditions for trigger
2024-06-04 4:24 UTC (10+ messages)
` [PATCH v4 1/4] target/riscv: Add functions for common matching conditions of trigger
` [PATCH v4 3/4] target/riscv: Apply modularized matching conditions for watchpoint
` [PATCH v4 4/4] target/riscv: Apply modularized matching conditions for icount trigger
[RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec
2024-06-04 3:56 UTC (14+ messages)
` [RESEND PATCH v2 1/5] target/riscv: Reuse the conversion function of priv_spec
` [RESEND PATCH v2 2/5] target/riscv: Support the version for ss1p13
` [RESEND PATCH v2 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0
` [RESEND PATCH v2 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
` [RESEND PATCH v2 5/5] target/riscv: Reserve exception codes for sw-check and hw-err
[PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
2024-06-04 3:41 UTC (4+ messages)
[PATCH] target/riscv: zvbb implies zvkb
2024-06-04 3:35 UTC (3+ messages)
` [PATCH v2] "
[PATCH 0/6] target/riscv: Support Zabha extension
2024-06-04 3:18 UTC (11+ messages)
` [PATCH 1/6] target/riscv: Move gen_amo before implement Zabha
` [PATCH 2/6] target/riscv: Add AMO instructions for Zabha
` [PATCH 3/6] target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
` [PATCH 4/6] target/riscv: Add amocas.[b|h] for Zabha
` [PATCH 6/6] disas/riscv: Support zabha disassemble
[PATCH 0/4] target/riscv: Implement May-Be-Operations(zimop) extension
2024-06-04 2:23 UTC (9+ messages)
` [PATCH 1/4] target/riscv: Add zimop extension
` [PATCH 2/4] disas/riscv: Support zimop disassemble
` [PATCH 3/4] target/riscv: Add zcmop extension
` [PATCH 4/4] disas/riscv: Support zcmop disassemble
[PATCH v2 0/2] target/riscv: Minor fixes and improvements for Virtual IRQs
2024-06-04 2:15 UTC (6+ messages)
` [PATCH v2 1/2] target/riscv: Extend virtual irq csrs masks to be 64 bit wide
` [PATCH v2 2/2] target/riscv: Move Guest irqs out of the core local irqs range
[PATCH] target/riscv: Fix mode in riscv_tlb_fill
2024-06-04 1:10 UTC (3+ messages)
` [PATCH v3 1/2] target/riscv/csr.c: Add functional of hvictl CSR
[PATCH] Fix incorrect disassembly format for certain RISC-V instructions
2024-06-04 1:05 UTC (3+ messages)
[RFC PATCH v2 0/6] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions
2024-06-04 0:58 UTC (5+ messages)
` [RFC PATCH v2 5/6] target/riscv: rvv: Optimize v[l|s]e8.v with limitations
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