From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: Rob Bradford <rbradford@rivosinc.com>,
qemu-devel@nongnu.org, Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
"open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH] target/riscv: Remove experimental prefix from "B" extension
Date: Fri, 10 May 2024 08:12:53 -0300 [thread overview]
Message-ID: <e7fd3556-1076-4a10-b9da-1ee894f8dd98@ventanamicro.com> (raw)
In-Reply-To: <20240510-bd3888b24a94d2a7cbbb9b96@orel>
On 5/10/24 05:29, Andrew Jones wrote:
> On Thu, May 09, 2024 at 02:23:42PM GMT, Daniel Henrique Barboza wrote:
>>
>>
>> On 5/8/24 08:22, Andrew Jones wrote:
>>> On Tue, May 07, 2024 at 11:27:21AM GMT, Rob Bradford wrote:
>>>> This extension has now been ratified:
>>>> https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
>>>> removed.
>>>>
>>>> Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
>>>> ---
>>>> target/riscv/cpu.c | 2 +-
>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>>>> index eb1a2e7d6d..861d9f4350 100644
>>>> --- a/target/riscv/cpu.c
>>>> +++ b/target/riscv/cpu.c
>>>> @@ -1396,7 +1396,7 @@ static const MISAExtInfo misa_ext_info_arr[] = {
>>>> MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
>>>> MISA_EXT_INFO(RVV, "v", "Vector operations"),
>>>> MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
>>>> - MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
>>>> + MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
>>>> };
>>>> static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
>>>> --
>>>> 2.44.0
>>>>
>>>>
>>>
>>> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>>>
>>> I think we should also either change the false to true for RVB in
>>> misa_ext_cfgs[] or at least ensure RVB is set for the 'max' cpu
>>> type in riscv_init_max_cpu_extensions().
>>
>> I prefer if we keep misa_ext_cfgs[] as is. Changing the defaults in this array
>> will also change the defaults for rv64. IMO we should enable RVB manually in
>> riscv_init_max_cpu_extensions().
>>
>> We already have some precedence for it: RVV is enabled in 'max' while is default
>> 'false' for rv64.
>
> But do we care if rv64 gets B? rv64 doesn't have any particular set of
> extensions, afaik. And B seems like it should be generally adopted enough
> to be in a "general" cpu type like rv64. Anyway, either way works for me
> as long as 'max' gets B one way or another.
Yes, as long as we enable it in 'max' it's good enough for this patch.
It's not like we're enabling extensions in rv64 just because they were ratified
(e.g. RVV isn't enabled in rv64), so even if we want to enable RVB in rv64 I'd
rather do it in a separated patch with a proper justification.
Thanks,
Daniel
>
> Thanks,
> drew
next prev parent reply other threads:[~2024-05-10 11:13 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-07 10:27 [PATCH] target/riscv: Remove experimental prefix from "B" extension Rob Bradford
2024-05-08 11:22 ` Andrew Jones
2024-05-09 17:23 ` Daniel Henrique Barboza
2024-05-10 8:29 ` Andrew Jones
2024-05-10 11:12 ` Daniel Henrique Barboza [this message]
2024-05-13 10:34 ` Alistair Francis
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