From: BALATON Zoltan <balaton@eik.bme.hu>
To: Nicholas Piggin <npiggin@gmail.com>
Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
Daniel Henrique Barboza <danielhb413@gmail.com>
Subject: Re: [PATCH v3 01/33] target/ppc: Fix gen_sc to use correct nip
Date: Wed, 8 May 2024 17:17:48 +0200 (CEST) [thread overview]
Message-ID: <e6a92c1b-8ecf-80e5-6095-8aa5d828d82c@eik.bme.hu> (raw)
In-Reply-To: <D14AXR65WIXZ.2H0R05J3AL0W4@gmail.com>
On Wed, 8 May 2024, Nicholas Piggin wrote:
> On Wed May 8, 2024 at 10:14 AM AEST, BALATON Zoltan wrote:
>> Most exceptions are raised with nip pointing to the faulting
>> instruction but the sc instruction generating a syscall exception
>> leaves nip pointing to next instruction. Fix gen_sc to not use
>> gen_exception_err() which sets nip back but correctly set nip to
>> pc_next so we don't have to patch this in the exception handlers.
>>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> target/ppc/excp_helper.c | 43 ++--------------------------------------
>> target/ppc/translate.c | 15 ++++++--------
>> 2 files changed, 8 insertions(+), 50 deletions(-)
>>
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index 0712098cf7..92fe535815 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -116,7 +116,7 @@ static void dump_syscall(CPUPPCState *env)
>> ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
>> ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
>> ppc_dump_gpr(env, 6), ppc_dump_gpr(env, 7),
>> - ppc_dump_gpr(env, 8), env->nip);
>> + ppc_dump_gpr(env, 8), env->nip - 4);
>> }
>>
>> static void dump_hcall(CPUPPCState *env)
>> @@ -131,7 +131,7 @@ static void dump_hcall(CPUPPCState *env)
>> ppc_dump_gpr(env, 7), ppc_dump_gpr(env, 8),
>> ppc_dump_gpr(env, 9), ppc_dump_gpr(env, 10),
>> ppc_dump_gpr(env, 11), ppc_dump_gpr(env, 12),
>> - env->nip);
>> + env->nip - 4);
>> }
>>
>> #ifdef CONFIG_TCG
>> @@ -516,12 +516,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
>> break;
>> case POWERPC_EXCP_SYSCALL: /* System call exception */
>> dump_syscall(env);
>> -
>> - /*
>> - * We need to correct the NIP which in this case is supposed
>> - * to point to the next instruction
>> - */
>> - env->nip += 4;
>> break;
>> case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
>> trace_ppc_excp_print("FIT");
>> @@ -632,12 +626,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
>> break;
>> case POWERPC_EXCP_SYSCALL: /* System call exception */
>> dump_syscall(env);
>> -
>> - /*
>> - * We need to correct the NIP which in this case is supposed
>> - * to point to the next instruction
>> - */
>> - env->nip += 4;
>> break;
>> case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
>> case POWERPC_EXCP_DECR: /* Decrementer exception */
>> @@ -780,13 +768,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
>> } else {
>> dump_syscall(env);
>> }
>> -
>> - /*
>> - * We need to correct the NIP which in this case is supposed
>> - * to point to the next instruction
>> - */
>> - env->nip += 4;
>> -
>> /*
>> * The Virtual Open Firmware (VOF) relies on the 'sc 1'
>> * instruction to communicate with QEMU. The pegasos2 machine
>> @@ -932,13 +913,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
>> } else {
>> dump_syscall(env);
>> }
>> -
>> - /*
>> - * We need to correct the NIP which in this case is supposed
>> - * to point to the next instruction
>> - */
>> - env->nip += 4;
>> -
>> /*
>> * The Virtual Open Firmware (VOF) relies on the 'sc 1'
>> * instruction to communicate with QEMU. The pegasos2 machine
>> @@ -1098,12 +1072,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
>> break;
>> case POWERPC_EXCP_SYSCALL: /* System call exception */
>> dump_syscall(env);
>> -
>> - /*
>> - * We need to correct the NIP which in this case is supposed
>> - * to point to the next instruction
>> - */
>> - env->nip += 4;
>> break;
>> case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
>> case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
>> @@ -1428,13 +1396,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
>> } else {
>> dump_syscall(env);
>> }
>> -
>> - /*
>> - * We need to correct the NIP which in this case is supposed
>> - * to point to the next instruction
>> - */
>> - env->nip += 4;
>> -
>> /* "PAPR mode" built-in hypercall emulation */
>> if (lev == 1 && books_vhyp_handles_hcall(cpu)) {
>> PPCVirtualHypervisorClass *vhc =
>> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
>> index 93ffec787c..e112c44a02 100644
>> --- a/target/ppc/translate.c
>> +++ b/target/ppc/translate.c
>> @@ -4472,22 +4472,19 @@ static void gen_hrfid(DisasContext *ctx)
>> #endif
>>
>> /* sc */
>> -#if defined(CONFIG_USER_ONLY)
>> -#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
>> -#else
>> -#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
>> -#endif
>> static void gen_sc(DisasContext *ctx)
>> {
>> - uint32_t lev;
>> -
>> /*
>> * LEV is a 7-bit field, but the top 6 bits are treated as a reserved
>> * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is
>> * for Ultravisor which TCG does not support, so just ignore the top 6.
>> */
>> - lev = (ctx->opcode >> 5) & 0x1;
>> - gen_exception_err(ctx, POWERPC_SYSCALL, lev);
>> + uint32_t lev = (ctx->opcode >> 5) & 0x1;
>> +#ifdef CONFIG_USER_ONLY
>> + gen_exception_err(ctx, POWERPC_EXCP_SYSCALL_USER, lev);
>> +#else
>> + gen_exception_err_nip(ctx, POWERPC_EXCP_SYSCALL, lev, ctx->base.pc_next);
>> +#endif
>
> I think this is the nail in the coffin for this one. Let's shelve it.
I really would like to get rid of all the +4s and long comments in
excp_helper.c though so I won't let this go until we find a solution. I've
now found that linux-user/ppc/cpu_loop.c handles this case and that also
has a +4 that I've missed before so with that removed this should work.
I'll try again.
Regards,
BALATON Zoltan
next prev parent reply other threads:[~2024-05-08 15:18 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-08 0:14 [PATCH v3 00/33] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
2024-05-08 0:14 ` [PATCH v3 01/33] target/ppc: Fix gen_sc to use correct nip BALATON Zoltan
2024-05-08 13:36 ` Nicholas Piggin
2024-05-08 15:17 ` BALATON Zoltan [this message]
2024-05-09 5:48 ` Nicholas Piggin
2024-05-08 0:14 ` [PATCH v3 02/33] target/ppc: Move patching nip from exception handler to helper_scv BALATON Zoltan
2024-05-08 0:14 ` [PATCH v3 03/33] target/ppc: Simplify syscall exception handlers BALATON Zoltan
2024-05-08 0:14 ` [PATCH v3 04/33] target/ppc: Remove unused helper BALATON Zoltan
2024-05-08 0:14 ` [PATCH v3 05/33] target/ppc/mmu_common.c: Move calculation of a value closer to its usage BALATON Zoltan
2024-05-08 0:14 ` [PATCH v3 06/33] target/ppc/mmu_common.c: Remove unneeded local variable BALATON Zoltan
2024-05-08 0:14 ` [PATCH v3 07/33] target/ppc/mmu_common.c: Simplify checking for real mode BALATON Zoltan
2024-05-08 0:15 ` [PATCH v3 08/33] target/ppc/mmu_common.c: Drop cases for unimplemented MPC8xx MMU BALATON Zoltan
2024-05-08 0:15 ` [PATCH v3 09/33] target/ppc/mmu_common.c: Introduce mmu6xx_get_physical_address() BALATON Zoltan
2024-05-08 12:40 ` Nicholas Piggin
2024-05-08 0:15 ` [PATCH v3 10/33] target/ppc/mmu_common.c: Move else branch to avoid large if block BALATON Zoltan
2024-05-08 12:43 ` Nicholas Piggin
2024-05-08 0:15 ` [PATCH v3 11/33] target/ppc/mmu_common.c: Move some debug logging BALATON Zoltan
2024-05-08 12:47 ` Nicholas Piggin
2024-05-08 0:15 ` [PATCH v3 12/33] target/ppc/mmu_common.c: Eliminate ret from mmu6xx_get_physical_address() BALATON Zoltan
2024-05-08 12:48 ` Nicholas Piggin
2024-05-08 0:15 ` [PATCH v3 13/33] target/ppc/mmu_common.c: Split out BookE cases before checking real mode BALATON Zoltan
2024-05-08 0:15 ` [PATCH v3 14/33] target/ppc/mmu_common.c: Split off real mode cases in get_physical_address_wtlb() BALATON Zoltan
2024-05-08 0:15 ` [PATCH v3 15/33] target/ppc/mmu_common.c: Inline and remove check_physical() BALATON Zoltan
2024-05-08 0:15 ` [PATCH v3 16/33] target/ppc/mmu_common.c: Simplify mmubooke_get_physical_address() BALATON Zoltan
2024-05-08 0:15 ` [PATCH v3 17/33] target/ppc/mmu_common.c: Simplify mmubooke206_get_physical_address() BALATON Zoltan
2024-05-08 0:15 ` [PATCH v3 18/33] target/ppc/mmu_common.c: Fix misindented qemu_log_mask() calls BALATON Zoltan
2024-05-08 0:15 ` [PATCH v3 19/33] target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate() BALATON Zoltan
2024-05-08 0:15 ` [PATCH v3 20/33] target/ppc/mmu_common.c: Replace hard coded constants in ppc_jumbo_xlate() BALATON Zoltan
2024-05-08 0:15 ` [PATCH v3 21/33] target/ppc/mmu_common.c: Make get_physical_address_wtlb() static BALATON Zoltan
2024-05-08 12:58 ` Nicholas Piggin
2024-05-08 0:15 ` [PATCH v3 22/33] target/ppc: Remove pp_check() and reuse ppc_hash32_pp_prot() BALATON Zoltan
2024-05-08 12:59 ` Nicholas Piggin
2024-05-08 0:15 ` [PATCH v3 23/33] target/ppc/mmu_common.c: Remove BookE from direct store handling BALATON Zoltan
2024-05-08 12:59 ` Nicholas Piggin
2024-05-08 0:15 ` [PATCH v3 24/33] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate() BALATON Zoltan
2024-05-08 13:01 ` Nicholas Piggin
2024-05-08 0:15 ` [PATCH v3 25/33] target/ppc/mmu_common.c: Remove BookE handling from get_physical_address_wtlb() BALATON Zoltan
2024-05-08 13:12 ` Nicholas Piggin
2024-05-08 0:15 ` [PATCH v3 26/33] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() part 1 BALATON Zoltan
2024-05-08 13:17 ` Nicholas Piggin
2024-05-08 15:25 ` BALATON Zoltan
2024-05-09 5:53 ` Nicholas Piggin
2024-05-08 0:15 ` [PATCH v3 27/33] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() part 2 BALATON Zoltan
2024-05-08 13:21 ` Nicholas Piggin
2024-05-08 0:15 ` [PATCH v3 28/33] target/ppc/mmu_common.c: Move BookE MMU functions together BALATON Zoltan
2024-05-08 13:21 ` Nicholas Piggin
2024-05-08 0:15 ` [PATCH v3 29/33] target/ppc: Remove id_tlbs flag from CPU env BALATON Zoltan
2024-05-08 0:15 ` [PATCH v3 30/33] target/ppc: Split off common embedded TLB init BALATON Zoltan
2024-05-08 0:15 ` [PATCH v3 31/33] target/ppc/mmu-hash32.c: Drop a local variable BALATON Zoltan
2024-05-08 13:22 ` Nicholas Piggin
2024-05-08 0:15 ` [PATCH v3 32/33] target/ppc/mmu-radix64.c: " BALATON Zoltan
2024-05-08 13:22 ` Nicholas Piggin
2024-05-08 0:15 ` [PATCH v3 33/33] target/ppc: Add a macro to check for page protection bit BALATON Zoltan
2024-05-08 13:29 ` Nicholas Piggin
2024-05-08 15:23 ` BALATON Zoltan
2024-05-09 5:52 ` Nicholas Piggin
2024-05-08 23:35 ` BALATON Zoltan
2024-05-09 5:58 ` Nicholas Piggin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=e6a92c1b-8ecf-80e5-6095-8aa5d828d82c@eik.bme.hu \
--to=balaton@eik.bme.hu \
--cc=danielhb413@gmail.com \
--cc=npiggin@gmail.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).