From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Frank Chang <frank.chang@sifive.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
ajones@ventanamicro.com, tjeznach@rivosinc.com
Subject: Re: [PATCH v2 11/15] hw/riscv/riscv-iommu: add DBG support
Date: Mon, 6 May 2024 10:05:09 -0300 [thread overview]
Message-ID: <e3eba1d7-35d7-4ecd-8443-320cbebc2bc3@ventanamicro.com> (raw)
In-Reply-To: <CANzO1D0ywHs+Juv9_qavykxCDiUsuk6tebObfSAyRbgW-WhGJA@mail.gmail.com>
Hi Frank,
On 5/6/24 01:09, Frank Chang wrote:
> Hi Daniel,
>
> Daniel Henrique Barboza <dbarboza@ventanamicro.com> 於 2024年3月8日 週五 上午12:05寫道：
>>
>> From: Tomasz Jeznach <tjeznach@rivosinc.com>
>>
>> DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
>> tr_response.
>>
>> The DBG cap is always enabled. No on/off toggle is provided for it.
>>
>> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>> hw/riscv/riscv-iommu-bits.h | 20 +++++++++++++
>> hw/riscv/riscv-iommu.c | 57 ++++++++++++++++++++++++++++++++++++-
>> 2 files changed, 76 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h
>> index 0994f5ce48..b3f92411bb 100644
>> --- a/hw/riscv/riscv-iommu-bits.h
>> +++ b/hw/riscv/riscv-iommu-bits.h
>> @@ -83,6 +83,7 @@ struct riscv_iommu_pq_record {
>> #define RISCV_IOMMU_CAP_MSI_MRIF BIT_ULL(23)
>> #define RISCV_IOMMU_CAP_ATS BIT_ULL(25)
>> #define RISCV_IOMMU_CAP_IGS GENMASK_ULL(29, 28)
>> +#define RISCV_IOMMU_CAP_DBG BIT_ULL(31)
>> #define RISCV_IOMMU_CAP_PAS GENMASK_ULL(37, 32)
>> #define RISCV_IOMMU_CAP_PD8 BIT_ULL(38)
>>
>> @@ -177,6 +178,25 @@ enum {
>> RISCV_IOMMU_INTR_COUNT
>> };
>>
>> +#define RISCV_IOMMU_IPSR_CIP BIT(RISCV_IOMMU_INTR_CQ)
>> +#define RISCV_IOMMU_IPSR_FIP BIT(RISCV_IOMMU_INTR_FQ)
>> +#define RISCV_IOMMU_IPSR_PMIP BIT(RISCV_IOMMU_INTR_PM)
>> +#define RISCV_IOMMU_IPSR_PIP BIT(RISCV_IOMMU_INTR_PQ)
>
> These are not related to the DBG.
>
>> +
>> +/* 5.24 Translation request IOVA (64bits) */
>> +#define RISCV_IOMMU_REG_TR_REQ_IOVA 0x0258
>> +
>> +/* 5.25 Translation request control (64bits) */
>> +#define RISCV_IOMMU_REG_TR_REQ_CTL 0x0260
>> +#define RISCV_IOMMU_TR_REQ_CTL_GO_BUSY BIT_ULL(0)
>> +#define RISCV_IOMMU_TR_REQ_CTL_PID GENMASK_ULL(31, 12)
>> +#define RISCV_IOMMU_TR_REQ_CTL_DID GENMASK_ULL(63, 40)
>> +
>> +/* 5.26 Translation request response (64bits) */
>> +#define RISCV_IOMMU_REG_TR_RESPONSE 0x0268
>> +#define RISCV_IOMMU_TR_RESPONSE_FAULT BIT_ULL(0)
>> +#define RISCV_IOMMU_TR_RESPONSE_PPN RISCV_IOMMU_PPN_FIELD
>> +
>> /* 5.27 Interrupt cause to vector (64bits) */
>> #define RISCV_IOMMU_REG_IVEC 0x02F8
>>
>> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
>> index 7af5929b10..1fa1286d07 100644
>> --- a/hw/riscv/riscv-iommu.c
>> +++ b/hw/riscv/riscv-iommu.c
>> @@ -1457,6 +1457,46 @@ static void riscv_iommu_process_pq_control(RISCVIOMMUState *s)
>> riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_PQCSR, ctrl_set, ctrl_clr);
>> }
>>
>> +static void riscv_iommu_process_dbg(RISCVIOMMUState *s)
>> +{
>> + uint64_t iova = riscv_iommu_reg_get64(s, RISCV_IOMMU_REG_TR_REQ_IOVA);
>> + uint64_t ctrl = riscv_iommu_reg_get64(s, RISCV_IOMMU_REG_TR_REQ_CTL);
>> + unsigned devid = get_field(ctrl, RISCV_IOMMU_TR_REQ_CTL_DID);
>> + unsigned pid = get_field(ctrl, RISCV_IOMMU_TR_REQ_CTL_PID);
>> + RISCVIOMMUContext *ctx;
>> + void *ref;
>> +
>> + if (!(ctrl & RISCV_IOMMU_TR_REQ_CTL_GO_BUSY)) {
>> + return;
>> + }
>> +
>> + ctx = riscv_iommu_ctx(s, devid, pid, &ref);
>> + if (ctx == NULL) {
>> + riscv_iommu_reg_set64(s, RISCV_IOMMU_REG_TR_RESPONSE,
>> + RISCV_IOMMU_TR_RESPONSE_FAULT |
>> + (RISCV_IOMMU_FQ_CAUSE_DMA_DISABLED << 10));
>> + } else {
>> + IOMMUTLBEntry iotlb = {
>> + .iova = iova,
>> + .perm = IOMMU_NONE,
>
> .perm should honor tr_req_ctl.[Exe|Nw]
>
>> + .addr_mask = ~0,
>> + .target_as = NULL,
>> + };
>> + int fault = riscv_iommu_translate(s, ctx, &iotlb, false);
>> + if (fault) {
>> + iova = RISCV_IOMMU_TR_RESPONSE_FAULT | (((uint64_t) fault) << 10);
>> + } else {
>> + iova = ((iotlb.translated_addr & ~iotlb.addr_mask) >> 2) &
>
> For 4-KB page, we should right-shift 12 bits.
>
>> + RISCV_IOMMU_TR_RESPONSE_PPN;
>
> It's possible that the translation is not 4-KB page (i.e. superpage),
> which we should set tr_response.S
> and encode translation range size in tr_response.PPN.
At this moment this emulation doesn't support superpages, at least from my
understanding. Tomasz is welcome to correct me if I'm wrong. I'll explictly
set tr_response.S to 0 here to make it clearer.
The idea here IIUC is to, in the future, merge the IOMMU translation lookup code
with the existing lookup code we have (cpu_helper.c, get_physical_address()), and
with that the IOMMU will end up supporting both super-pages and svnapot.
Thanks,
Daniel
>
> Regards,
> Frank Chang
>
>> + }
>> + riscv_iommu_reg_set64(s, RISCV_IOMMU_REG_TR_RESPONSE, iova);
>> + }
>> +
>> + riscv_iommu_reg_mod64(s, RISCV_IOMMU_REG_TR_REQ_CTL, 0,
>> + RISCV_IOMMU_TR_REQ_CTL_GO_BUSY);
>> + riscv_iommu_ctx_put(s, ref);
>> +}
>> +
>> /* Core IOMMU execution activation */
>> enum {
>> RISCV_IOMMU_EXEC_DDTP,
>> @@ -1502,7 +1542,7 @@ static void *riscv_iommu_core_proc(void* arg)
>> /* NOP */
>> break;
>> case BIT(RISCV_IOMMU_EXEC_TR_REQUEST):
>> - /* DBG support not implemented yet */
>> + riscv_iommu_process_dbg(s);
>> break;
>> }
>> exec &= ~mask;
>> @@ -1574,6 +1614,12 @@ static MemTxResult riscv_iommu_mmio_write(void *opaque, hwaddr addr,
>> exec = BIT(RISCV_IOMMU_EXEC_PQCSR);
>> busy = RISCV_IOMMU_PQCSR_BUSY;
>> break;
>> +
>> + case RISCV_IOMMU_REG_TR_REQ_CTL:
>> + exec = BIT(RISCV_IOMMU_EXEC_TR_REQUEST);
>> + regb = RISCV_IOMMU_REG_TR_REQ_CTL;
>> + busy = RISCV_IOMMU_TR_REQ_CTL_GO_BUSY;
>> + break;
>> }
>>
>> /*
>> @@ -1746,6 +1792,9 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
>> s->cap |= RISCV_IOMMU_CAP_SV32X4 | RISCV_IOMMU_CAP_SV39X4 |
>> RISCV_IOMMU_CAP_SV48X4 | RISCV_IOMMU_CAP_SV57X4;
>> }
>> + /* Enable translation debug interface */
>> + s->cap |= RISCV_IOMMU_CAP_DBG;
>> +
>> /* Report QEMU target physical address space limits */
>> s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS,
>> TARGET_PHYS_ADDR_SPACE_BITS);
>> @@ -1800,6 +1849,12 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
>> stl_le_p(&s->regs_wc[RISCV_IOMMU_REG_IPSR], ~0);
>> stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_IVEC], 0);
>> stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_DDTP], s->ddtp);
>> + /* If debug registers enabled. */
>> + if (s->cap & RISCV_IOMMU_CAP_DBG) {
>> + stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_TR_REQ_IOVA], 0);
>> + stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_TR_REQ_CTL],
>> + RISCV_IOMMU_TR_REQ_CTL_GO_BUSY);
>> + }
>>
>> /* Memory region for downstream access, if specified. */
>> if (s->target_mr) {
>> --
>> 2.43.2
>>
>>
next prev parent reply other threads:[~2024-05-06 13:07 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-07 16:03 [PATCH v2 00/15] riscv: QEMU RISC-V IOMMU Support Daniel Henrique Barboza
2024-03-07 16:03 ` [PATCH v2 01/15] exec/memtxattr: add process identifier to the transaction attributes Daniel Henrique Barboza
2024-04-23 16:33 ` Frank Chang
2024-03-07 16:03 ` [PATCH v2 02/15] hw/riscv: add riscv-iommu-bits.h Daniel Henrique Barboza
2024-05-10 11:01 ` Frank Chang
2024-05-15 10:02 ` Eric Cheng
2024-05-15 14:28 ` Daniel Henrique Barboza
2024-03-07 16:03 ` [PATCH v2 03/15] hw/riscv: add RISC-V IOMMU base emulation Daniel Henrique Barboza
2024-05-01 11:57 ` Jason Chien
2024-05-14 20:06 ` Daniel Henrique Barboza
2024-05-02 11:37 ` Frank Chang
2024-05-08 11:15 ` Daniel Henrique Barboza
2024-05-10 10:58 ` Frank Chang
2024-05-13 12:41 ` Daniel Henrique Barboza
2024-05-13 12:37 ` Daniel Henrique Barboza
2024-05-16 7:13 ` Frank Chang
2024-05-20 16:17 ` Daniel Henrique Barboza
2024-05-21 10:52 ` Frank Chang
2024-05-21 12:28 ` Daniel Henrique Barboza
2024-03-07 16:03 ` [PATCH v2 04/15] hw/riscv: add riscv-iommu-pci device Daniel Henrique Barboza
2024-04-29 7:21 ` Frank Chang
2024-05-02 9:37 ` Daniel Henrique Barboza
2024-03-07 16:03 ` [PATCH v2 05/15] hw/riscv: add riscv-iommu-sys platform device Daniel Henrique Barboza
2024-04-30 1:35 ` Frank Chang
2024-03-07 16:03 ` [PATCH v2 06/15] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug Daniel Henrique Barboza
2024-04-30 2:17 ` Frank Chang
2024-05-15 6:25 ` Eric Cheng
2024-05-15 7:16 ` Andrew Jones
2024-03-07 16:03 ` [PATCH v2 07/15] test/qtest: add riscv-iommu-pci tests Daniel Henrique Barboza
2024-04-30 3:33 ` Frank Chang
2024-03-07 16:03 ` [PATCH v2 08/15] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) Daniel Henrique Barboza
2024-05-08 7:26 ` Frank Chang
2024-05-16 21:45 ` Daniel Henrique Barboza
2024-03-07 16:03 ` [PATCH v2 09/15] hw/riscv/riscv-iommu: add s-stage and g-stage support Daniel Henrique Barboza
2024-05-10 10:36 ` Frank Chang
2024-05-10 11:14 ` Andrew Jones
2024-05-16 19:41 ` Daniel Henrique Barboza
2024-03-07 16:03 ` [PATCH v2 10/15] hw/riscv/riscv-iommu: add ATS support Daniel Henrique Barboza
2024-05-08 2:57 ` Frank Chang
2024-05-17 9:29 ` Daniel Henrique Barboza
2024-03-07 16:03 ` [PATCH v2 11/15] hw/riscv/riscv-iommu: add DBG support Daniel Henrique Barboza
2024-05-06 4:09 ` Frank Chang
2024-05-06 13:05 ` Daniel Henrique Barboza [this message]
2024-05-10 10:59 ` Frank Chang
2024-03-07 16:03 ` [PATCH v2 12/15] hw/riscv/riscv-iommu: Add another irq for mrif notifications Daniel Henrique Barboza
2024-05-06 6:12 ` Frank Chang
2024-03-07 16:03 ` [PATCH v2 13/15] qtest/riscv-iommu-test: add init queues test Daniel Henrique Barboza
2024-05-07 8:01 ` Frank Chang
2024-03-07 16:03 ` [PATCH v2 14/15] hw/misc: EDU: added PASID support Daniel Henrique Barboza
2024-05-07 9:06 ` Frank Chang
2024-03-07 16:03 ` [PATCH v2 15/15] hw/misc: EDU: add ATS/PRI capability Daniel Henrique Barboza
2024-05-07 15:32 ` Frank Chang
2024-05-16 13:59 ` Daniel Henrique Barboza
2024-05-10 11:14 ` [PATCH v2 00/15] riscv: QEMU RISC-V IOMMU Support Frank Chang
2024-05-20 16:26 ` Daniel Henrique Barboza
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