From: Richard Henderson <richard.henderson@linaro.org>
To: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Cc: qemu-devel@nongnu.org, bcain@quicinc.com, sidneym@quicinc.com,
ale@rev.ng, anjo@rev.ng, ltaylorsimpson@gmail.com,
laurent@vivier.eu
Subject: Re: [PATCH v5] Hexagon: add PC alignment check and exception
Date: Fri, 3 May 2024 07:56:56 -0700 [thread overview]
Message-ID: <d394161d-9e88-45dc-9f72-e07e4d8803e2@linaro.org> (raw)
In-Reply-To: <20240503134635.78067-1-quic_mathbern@quicinc.com>
On 5/3/24 06:38, Matheus Tavares Bernardino wrote:
> On Thu, 2 May 2024 13:00:34 -0700 Richard Henderson <richard.henderson@linaro.org> wrote:
>>
>> On 5/2/24 12:20, Matheus Tavares Bernardino wrote:
>>>
>>> +
>>> +void test_multi_cof(void)
>>> +{
>>> + asm volatile(
>>> + "p0 = cmp.eq(r0, r0)\n"
>>> + "{\n"
>>> + " if (p0) jump test_multi_cof_unaligned\n"
>>> + " if (!p0) jump 1f\n"
>>> + "}\n"
>>> + "1: nop\n"
>>
>> Does it work to write "jump 1f+1" or something?
>
> Unfortunately no :( The assembler will align the address when encoding the
> instruction. The only working examples I could think of is using a separated
> file, like before, or manually encoding the instruction with a misaligned
> address and place it with a `.word` directive... Any preferences, or other
> suggestions?
Oof. The assembler is being too helpful. :-P
Perhaps using a different section could solve the fragility issue:
asm("
.pushsection .text.evil
.org 3
...
.popsection
");
(adjusting syntax as necessary for correctness), then it doesn't matter where in the
output assembly the fragment lands.
r~
prev parent reply other threads:[~2024-05-03 14:58 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-02 19:20 [PATCH v5] Hexagon: add PC alignment check and exception Matheus Tavares Bernardino
2024-05-02 20:00 ` Richard Henderson
2024-05-03 13:38 ` Matheus Tavares Bernardino
2024-05-03 14:56 ` Richard Henderson [this message]
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