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Thu, 10 Jun 2021 16:22:32 -0700 (PDT) MIME-Version: 1.0 References: <20210610144424.8658-1-ruinland@andestech.com> <20210610144424.8658-2-ruinland@andestech.com> In-Reply-To: <20210610144424.8658-2-ruinland@andestech.com> From: Bin Meng Date: Fri, 11 Jun 2021 07:22:21 +0800 Message-ID: Subject: Re: [RFC PATCH v3 1/2] Adding Andes AX25 CPU model To: Ruinland Chuan-Tzu Tsai Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b32; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dylan Jhong , "open list:RISC-V" , Alan Kao , wangjunqiang , Bin Meng , "qemu-devel@nongnu.org Developers" , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Ruinland, On Thu, Jun 10, 2021 at 10:45 PM Ruinland Chuan-Tzu Tsai wrote: > > From: Ruinaldn ChuanTzu Tsai > > Adding the skeleton of Andes Technology AX25 CPU model for the future commits, > which will utilize custom/vendor CSR handling mechaism. typo: mechanism > --- > target/riscv/cpu.c | 8 ++++++++ > target/riscv/cpu.h | 1 + > 2 files changed, 9 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ddea8fbeeb..4ae21cbf9b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -159,6 +159,13 @@ static void rv64_base_cpu_init(Object *obj) > set_misa(env, RV64); > } > > +static void ax25_cpu_init(Object *obj) > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > +} > + > static void rv64_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > @@ -705,6 +712,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), > #elif defined(TARGET_RISCV64) > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_AX25, ax25_cpu_init), What about the 32-bit variant of A25, and the SMP variant of A25MP/AX25MP? Also how about the latest A45 (RV32) and AX45 (RV64)? How should we name these? I think we may need to name this using the SMP variant name, no? > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), > #endif Regards, Bin