From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: qemu-devel@nongnu.org
Cc: "Huacai Chen" <chenhuacai@kernel.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Song Gao" <gaosong@loongson.cn>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>
Subject: [PATCH 3/5] hw/intc/loongson_ipi: Implement IOCSR address space for MIPS
Date: Wed, 08 May 2024 14:06:48 +0100 [thread overview]
Message-ID: <20240508-loongson3-ipi-v1-3-1a7b67704664@flygoat.com> (raw)
In-Reply-To: <20240508-loongson3-ipi-v1-0-1a7b67704664@flygoat.com>
Implement IOCSR address space get functions for MIPS/Loongson CPUs.
For MIPS/Loongson without IOCSR (i.e. Loongson-3A1000), get_cpu_iocsr_as
will return as null, and send_ipi_data will fail with MEMTX_DECODE_ERROR,
which matches expected behavior on hardware.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
I understand that there was a review comment stating that I shouldn't
use TARGET_* macros in device drivers. But I still think this is the
best way to handle architectural difference. There are many TARGET_*
usages in hw/virtio for similiar purpose.
---
hw/intc/loongson_ipi.c | 39 ++++++++++++++++++++++++++++++---------
1 file changed, 30 insertions(+), 9 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 8c888da3b27c..93cc50a37a11 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -15,7 +15,12 @@
#include "qemu/log.h"
#include "exec/address-spaces.h"
#include "migration/vmstate.h"
+#ifdef TARGET_LOONGARCH64
#include "target/loongarch/cpu.h"
+#endif
+#ifdef TARGET_MIPS
+#include "target/mips/cpu.h"
+#endif
#include "trace.h"
static MemTxResult loongson_ipi_readl(void *opaque, hwaddr addr,
@@ -56,18 +61,35 @@ static MemTxResult loongson_ipi_readl(void *opaque, hwaddr addr,
return MEMTX_OK;
}
-static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr,
+static AddressSpace *get_cpu_iocsr_as(CPUState *cpu)
+{
+#ifdef TARGET_LOONGARCH64
+ return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
+#endif
+#ifdef TARGET_MIPS
+ if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) {
+ return &MIPS_CPU(cpu)->env.iocsr.as;
+ }
+#endif
+ return NULL;
+}
+
+static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr,
MemTxAttrs attrs)
{
int i, mask = 0, data = 0;
+ AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu);
+
+ if (!iocsr_as) {
+ return MEMTX_DECODE_ERROR;
+ }
/*
* bit 27-30 is mask for byte writing,
* if the mask is 0, we need not to do anything.
*/
if ((val >> 27) & 0xf) {
- data = address_space_ldl(env->address_space_iocsr, addr,
- attrs, NULL);
+ data = address_space_ldl(iocsr_as, addr, attrs, NULL);
for (i = 0; i < 4; i++) {
/* get mask for byte writing */
if (val & (0x1 << (27 + i))) {
@@ -78,8 +100,9 @@ static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr,
data &= mask;
data |= (val >> 32) & ~mask;
- address_space_stl(env->address_space_iocsr, addr,
- data, attrs, NULL);
+ address_space_stl(iocsr_as, addr, data, attrs, NULL);
+
+ return MEMTX_OK;
}
static int archid_cmp(const void *a, const void *b)
@@ -130,8 +153,7 @@ static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs)
/* override requester_id */
addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
attrs.requester_id = cs->cpu_index;
- send_ipi_data(&LOONGARCH_CPU(cs)->env, val, addr, attrs);
- return MEMTX_OK;
+ return send_ipi_data(cs, val, addr, attrs);
}
static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
@@ -149,8 +171,7 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
/* override requester_id */
addr = val & 0xffff;
attrs.requester_id = cs->cpu_index;
- send_ipi_data(&LOONGARCH_CPU(cs)->env, val, addr, attrs);
- return MEMTX_OK;
+ return send_ipi_data(cs, val, addr, attrs);
}
static MemTxResult loongson_ipi_writel(void *opaque, hwaddr addr, uint64_t val,
--
2.34.1
next prev parent reply other threads:[~2024-05-08 13:07 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-08 13:06 [PATCH 0/5] hw/mips/loongson3_virt: Implement IPI support Jiaxun Yang
2024-05-08 13:06 ` [PATCH 1/5] hw/intc/loongarch_ipi: Remove pointless MAX_CPU check Jiaxun Yang
2024-05-08 16:22 ` Philippe Mathieu-Daudé
2024-05-08 13:06 ` [PATCH 2/5] hw/intc/loongarch_ipi: Rename as loongson_ipi Jiaxun Yang
2024-05-08 16:24 ` Philippe Mathieu-Daudé
2024-05-08 13:06 ` Jiaxun Yang [this message]
2024-05-08 16:21 ` [PATCH 3/5] hw/intc/loongson_ipi: Implement IOCSR address space for MIPS Philippe Mathieu-Daudé
2024-06-03 15:45 ` Philippe Mathieu-Daudé
2024-06-04 10:35 ` Jiaxun Yang
2024-06-04 12:37 ` gaosong
2024-05-08 13:06 ` [PATCH 4/5] hw/intc/loongson_ipi: Provide per core MMIO address spaces Jiaxun Yang
2024-05-08 13:06 ` [PATCH 5/5] hw/mips/loongson3_virt: Wire up loongson_ipi device Jiaxun Yang
2024-06-03 15:46 ` Philippe Mathieu-Daudé
2024-05-08 21:41 ` [PATCH 0/5] hw/mips/loongson3_virt: Implement IPI support Philippe Mathieu-Daudé
2024-05-16 10:53 ` Jiaxun Yang
2024-06-03 15:35 ` Philippe Mathieu-Daudé
2024-06-04 12:55 ` gaosong
2024-06-04 14:24 ` Philippe Mathieu-Daudé
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