From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>
Subject: [PULL 22/26] target/i386: port extensions of one-byte opcodes to new decoder
Date: Tue, 7 May 2024 12:55:34 +0200 [thread overview]
Message-ID: <20240507105538.180704-23-pbonzini@redhat.com> (raw)
In-Reply-To: <20240507105538.180704-1-pbonzini@redhat.com>
A few two-byte opcodes are simple extensions of existing one-byte opcodes;
they are easy to decode and need no change to emit.c.inc. Port them to
the new decoder.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 4 ++++
target/i386/tcg/decode-new.c.inc | 20 ++++++++++++++++++++
target/i386/tcg/emit.c.inc | 15 +++++++++++++++
3 files changed, 39 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 751ec5d0f1a..4fbd91e70d1 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -3209,6 +3209,10 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
#endif
if (use_new &&
((b >= 0x138 && b <= 0x19f) ||
+ (b & ~9) == 0x1a0 ||
+ b == 0x1af || b == 0x1b2 ||
+ (b >= 0x1b4 && b <= 0x1b7) ||
+ b == 0x1be || b == 0x1bf || b == 0x1c3 ||
(b >= 0x1c8 && b <= 0x1cf))) {
disas_insn_new(s, cpu, b);
return true;
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 16e23ec3d88..f9a966943fb 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -1053,6 +1053,9 @@ static const X86OpEntry opcodes_0F[256] = {
[0x96] = X86_OP_ENTRYw(SETcc, E,b),
[0x97] = X86_OP_ENTRYw(SETcc, E,b),
+ [0xa0] = X86_OP_ENTRYr(PUSH, FS, w),
+ [0xa1] = X86_OP_ENTRYw(POP, FS, w),
+
[0x28] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1 p_00_66), /* MOVAPS */
[0x29] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 p_00_66), /* MOVAPS */
[0x2A] = X86_OP_GROUP0(0F2A),
@@ -1117,9 +1120,26 @@ static const X86OpEntry opcodes_0F[256] = {
[0x9e] = X86_OP_ENTRYw(SETcc, E,b),
[0x9f] = X86_OP_ENTRYw(SETcc, E,b),
+ [0xa8] = X86_OP_ENTRYr(PUSH, GS, w),
+ [0xa9] = X86_OP_ENTRYw(POP, GS, w),
[0xae] = X86_OP_GROUP0(group15),
+ /*
+ * It's slightly more efficient to put Ev operand in T0 and allow gen_IMUL3
+ * to assume sextT0. Multiplication is commutative anyway.
+ */
+ [0xaf] = X86_OP_ENTRY3(IMUL3, G,v, E,v, 2op,v, sextT0),
+
+ [0xb2] = X86_OP_ENTRY3(LSS, G,v, EM,p, None, None),
+ [0xb4] = X86_OP_ENTRY3(LFS, G,v, EM,p, None, None),
+ [0xb5] = X86_OP_ENTRY3(LGS, G,v, EM,p, None, None),
+ [0xb6] = X86_OP_ENTRY3(MOV, G,v, E,b, None, None, zextT0), /* MOVZX */
+ [0xb7] = X86_OP_ENTRY3(MOV, G,v, E,w, None, None, zextT0), /* MOVZX */
+
+ [0xbe] = X86_OP_ENTRY3(MOV, G,v, E,b, None, None, sextT0), /* MOVSX */
+ [0xbf] = X86_OP_ENTRY3(MOV, G,v, E,w, None, None, sextT0), /* MOVSX */
[0xc2] = X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
+ [0xc3] = X86_OP_ENTRY3(MOV, EM,y,G,y, None,None, cpuid(SSE2)), /* MOVNTI */
[0xc4] = X86_OP_ENTRY4(PINSRW, V,dq,H,dq,E,w, vex5 mmx p_00_66),
[0xc5] = X86_OP_ENTRY3(PEXTRW, G,d, U,dq,I,b, vex5 mmx p_00_66),
[0xc6] = X86_OP_ENTRY4(VSHUF, V,x, H,x, W,x, vex4 p_00_66),
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index befde6677be..58f255873ff 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -1979,6 +1979,16 @@ static void gen_LES(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_lxx_seg(s, env, decode, R_ES);
}
+static void gen_LFS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_lxx_seg(s, env, decode, R_FS);
+}
+
+static void gen_LGS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_lxx_seg(s, env, decode, R_GS);
+}
+
static void gen_LODS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
MemOp ot = decode->op[2].ot;
@@ -2023,6 +2033,11 @@ static void gen_LOOPNE(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode
gen_conditional_jump_labels(s, decode->immediate, not_taken, taken);
}
+static void gen_LSS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_lxx_seg(s, env, decode, R_SS);
+}
+
static void gen_MOV(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
/* nothing to do! */
--
2.45.0
next prev parent reply other threads:[~2024-05-07 10:57 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-07 10:55 [PULL 00/26] target/i386 changes for 2024-05-07 Paolo Bonzini
2024-05-07 10:55 ` [PULL 01/26] target/i386: Fix CPUID encoding of Fn8000001E_ECX Paolo Bonzini
2024-05-07 10:55 ` [PULL 02/26] target/i386: use TSTEQ/TSTNE to test low bits Paolo Bonzini
2024-05-07 10:55 ` [PULL 03/26] target/i386: use TSTEQ/TSTNE to check flags Paolo Bonzini
2024-05-07 10:55 ` [PULL 04/26] target/i386: remove mask from CCPrepare Paolo Bonzini
2024-05-07 10:55 ` [PULL 05/26] target/i386: cc_op is not dynamic in gen_jcc1 Paolo Bonzini
2024-05-07 10:55 ` [PULL 06/26] target/i386: cleanup cc_op changes for REP/REPZ/REPNZ Paolo Bonzini
2024-05-07 10:55 ` [PULL 07/26] target/i386: pull cc_op update to callers of gen_jmp_rel{, _csize} Paolo Bonzini
2024-05-07 10:55 ` [PULL 08/26] target/i386: extend cc_* when using them to compute flags Paolo Bonzini
2024-05-07 10:55 ` [PULL 09/26] target/i386: do not use s->T0 and s->T1 as scratch registers for CCPrepare Paolo Bonzini
2024-05-07 10:55 ` [PULL 10/26] target/i386: clarify the "reg" argument of functions returning CCPrepare Paolo Bonzini
2024-05-07 10:55 ` [PULL 11/26] target/i386: cleanup *gen_eob* Paolo Bonzini
2024-05-07 10:55 ` [PULL 12/26] target/i386: reintroduce debugging mechanism Paolo Bonzini
2024-05-07 10:55 ` [PULL 13/26] target/i386: move 00-5F opcodes to new decoder Paolo Bonzini
2024-05-07 10:55 ` [PULL 14/26] target/i386: extract gen_far_call/jmp, reordering temporaries Paolo Bonzini
2024-05-07 10:55 ` [PULL 15/26] target/i386: allow instructions with more than one immediate Paolo Bonzini
2024-05-07 10:55 ` [PULL 16/26] target/i386: move 60-BF opcodes to new decoder Paolo Bonzini
2024-05-07 10:55 ` [PULL 17/26] target/i386: generalize gen_movl_seg_T0 Paolo Bonzini
2024-05-07 10:55 ` [PULL 18/26] target/i386: move C0-FF opcodes to new decoder (except for x87) Paolo Bonzini
2024-05-07 10:55 ` [PULL 19/26] target/i386: merge and enlarge a few ranges for call to disas_insn_new Paolo Bonzini
2024-05-07 10:55 ` [PULL 20/26] target/i386: move remaining conditional operations to new decoder Paolo Bonzini
2024-05-07 10:55 ` [PULL 21/26] target/i386: move BSWAP " Paolo Bonzini
2024-05-07 10:55 ` Paolo Bonzini [this message]
2024-05-07 10:55 ` [PULL 23/26] target/i386: remove now-converted opcodes from old decoder Paolo Bonzini
2024-05-07 10:55 ` [PULL 24/26] target/i386: decode x87 instructions in a separate function Paolo Bonzini
2024-05-07 10:55 ` [PULL 25/26] target/i386: split legacy decoder into " Paolo Bonzini
2024-05-07 10:55 ` [PULL 26/26] target/i386: remove duplicate prefix decoding Paolo Bonzini
2024-05-07 18:27 ` [PULL 00/26] target/i386 changes for 2024-05-07 Richard Henderson
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