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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, zhao1.liu@intel.com
Subject: [PATCH v2 24/25] target/i386: split legacy decoder into a separate function
Date: Mon,  6 May 2024 10:09:56 +0200	[thread overview]
Message-ID: <20240506080957.10005-25-pbonzini@redhat.com> (raw)
In-Reply-To: <20240506080957.10005-1-pbonzini@redhat.com>

Split the bits that have some duplication with disas_insn_new, from
those that should be the main topic of the conversion.  This is the
first step towards removing duplicate decoding of prefixes between
disas_insn and disas_insn_new.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/tcg/translate.c | 58 +++++++++++++++++++++++--------------
 1 file changed, 37 insertions(+), 21 deletions(-)

diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index e077fdd8c71..8c1062c8e13 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -3116,15 +3116,15 @@ static bool disas_insn_x87(DisasContext *s, CPUState *cpu, int b)
     return true;
 }
 
+static void disas_insn_old(DisasContext *s, CPUState *cpu, int b);
+
 /* convert one instruction. s->base.is_jmp is set if the translation must
    be stopped. Return the next pc value */
 static bool disas_insn(DisasContext *s, CPUState *cpu)
 {
     CPUX86State *env = cpu_env(cpu);
     int b, prefixes;
-    int shift;
-    MemOp ot, aflag, dflag;
-    int modrm, reg, rm, mod, op, opreg, val;
+    MemOp aflag, dflag;
     bool orig_cc_op_dirty = s->cc_op_dirty;
     CCOp orig_cc_op = s->cc_op;
     target_ulong orig_pc_save = s->pc_save;
@@ -3270,6 +3270,38 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
     s->aflag = aflag;
     s->dflag = dflag;
 
+    switch (b) {
+    case 0     ... 0xd7:
+    case 0xe0  ... 0xff:
+    case 0x10e ... 0x117:
+    case 0x128 ... 0x12f:
+    case 0x138 ... 0x19f:
+    case 0x1a0 ... 0x1a1:
+    case 0x1a8 ... 0x1a9:
+    case 0x1af:
+    case 0x1b2:
+    case 0x1b4 ... 0x1b7:
+    case 0x1be ... 0x1bf:
+    case 0x1c2 ... 0x1c6:
+    case 0x1c8 ... 0x1ff:
+        disas_insn_new(s, cpu, b);
+        break;
+    default:
+        disas_insn_old(s, cpu, b);
+        break;
+    }
+    return true;
+}
+
+static void disas_insn_old(DisasContext *s, CPUState *cpu, int b)
+{
+    CPUX86State *env = cpu_env(cpu);
+    int prefixes = s->prefix;
+    MemOp dflag = s->dflag;
+    int shift;
+    MemOp ot;
+    int modrm, reg, rm, mod, op, opreg, val;
+
     /* now check op code */
     switch (b) {
         /**************************/
@@ -4725,31 +4757,15 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
 
         set_cc_op(s, CC_OP_POPCNT);
         break;
-    case 0     ... 0xd7:
-    case 0xe0  ... 0xff:
-    case 0x10e ... 0x117:
-    case 0x128 ... 0x12f:
-    case 0x138 ... 0x19f:
-    case 0x1a0 ... 0x1a1:
-    case 0x1a8 ... 0x1a9:
-    case 0x1af:
-    case 0x1b2:
-    case 0x1b4 ... 0x1b7:
-    case 0x1be ... 0x1bf:
-    case 0x1c2 ... 0x1c6:
-    case 0x1c8 ... 0x1ff:
-        disas_insn_new(s, cpu, b);
-        break;
     default:
         goto unknown_op;
     }
-    return true;
+    return;
  illegal_op:
     gen_illegal_opcode(s);
-    return true;
+    return;
  unknown_op:
     gen_unknown_opcode(env, s);
-    return true;
 }
 
 void tcg_x86_init(void)
-- 
2.45.0



  parent reply	other threads:[~2024-05-06  8:15 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-06  8:09 [PATCH v2 00/25] target/i386: convert 1-byte opcodes to new decoder Paolo Bonzini
2024-05-06  8:09 ` [PATCH v2 01/25] target/i386: use TSTEQ/TSTNE to test low bits Paolo Bonzini
2024-05-06  8:09 ` [PATCH v2 02/25] target/i386: use TSTEQ/TSTNE to check flags Paolo Bonzini
2024-05-06  8:09 ` [PATCH v2 03/25] target/i386: remove mask from CCPrepare Paolo Bonzini
2024-05-06  8:09 ` [PATCH v2 04/25] target/i386: cc_op is not dynamic in gen_jcc1 Paolo Bonzini
2024-05-06 15:53   ` Richard Henderson
2024-05-06  8:09 ` [PATCH v2 05/25] target/i386: cleanup cc_op changes for REP/REPZ/REPNZ Paolo Bonzini
2024-05-06 16:07   ` Richard Henderson
2024-05-06 16:31     ` Paolo Bonzini
2024-05-06 16:39       ` Richard Henderson
2024-05-06  8:09 ` [PATCH v2 06/25] target/i386: pull cc_op update to callers of gen_jmp_rel{, _csize} Paolo Bonzini
2024-05-06 16:12   ` [PATCH v2 06/25] target/i386: pull cc_op update to callers of gen_jmp_rel{,_csize} Richard Henderson
2024-05-06  8:09 ` [PATCH v2 07/25] target/i386: extend cc_* when using them to compute flags Paolo Bonzini
2024-05-06 16:16   ` Richard Henderson
2024-05-06  8:09 ` [PATCH v2 08/25] target/i386: do not use s->T0 and s->T1 as scratch registers for CCPrepare Paolo Bonzini
2024-05-06 16:18   ` Richard Henderson
2024-05-06  8:09 ` [PATCH v2 09/25] target/i386: clarify the "reg" argument of functions returning CCPrepare Paolo Bonzini
2024-05-06 16:19   ` Richard Henderson
2024-05-06  8:09 ` [PATCH v2 10/25] target/i386: cleanup *gen_eob* Paolo Bonzini
2024-05-06 16:21   ` Richard Henderson
2024-05-06  8:09 ` [PATCH v2 11/25] target/i386: reintroduce debugging mechanism Paolo Bonzini
2024-05-06 16:23   ` Richard Henderson
2024-05-06  8:09 ` [PATCH v2 12/25] target/i386: move 00-5F opcodes to new decoder Paolo Bonzini
2024-05-06  8:09 ` [PATCH v2 13/25] target/i386: extract gen_far_call/jmp, reordering temporaries Paolo Bonzini
2024-05-06  8:09 ` [PATCH v2 14/25] target/i386: allow instructions with more than one immediate Paolo Bonzini
2024-05-06  8:09 ` [PATCH v2 15/25] target/i386: move 60-BF opcodes to new decoder Paolo Bonzini
2024-05-06 16:44   ` Richard Henderson
2024-05-06  8:09 ` [PATCH v2 16/25] target/i386: generalize gen_movl_seg_T0 Paolo Bonzini
2024-05-06  8:09 ` [PATCH v2 17/25] target/i386: move C0-FF opcodes to new decoder (except for x87) Paolo Bonzini
2024-05-06 16:56   ` Richard Henderson
2024-05-06  8:09 ` [PATCH v2 18/25] target/i386: merge and enlarge a few ranges for call to disas_insn_new Paolo Bonzini
2024-05-06  8:09 ` [PATCH v2 19/25] target/i386: move remaining conditional operations to new decoder Paolo Bonzini
2024-05-06  8:09 ` [PATCH v2 20/25] target/i386: move BSWAP " Paolo Bonzini
2024-05-06  8:09 ` [PATCH v2 21/25] target/i386: port extensions of one-byte opcodes " Paolo Bonzini
2024-05-06  8:09 ` [PATCH v2 22/25] target/i386: remove now-converted opcodes from old decoder Paolo Bonzini
2024-05-06  8:09 ` [PATCH v2 23/25] target/i386: decode x87 instructions in a separate function Paolo Bonzini
2024-05-06  8:09 ` Paolo Bonzini [this message]
2024-05-06  8:09 ` [PATCH v2 25/25] target/i386: remove duplicate prefix decoding Paolo Bonzini

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