* [PULL 0/4] M68k for 6.1 patches
@ 2021-05-26 19:57 Laurent Vivier
2021-05-26 19:57 ` [PULL 1/4] target/m68k: introduce is_singlestepping() function Laurent Vivier
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Laurent Vivier @ 2021-05-26 19:57 UTC (permalink / raw
To: qemu-devel; +Cc: Laurent Vivier
The following changes since commit 0319ad22bd5789e1eaa8a2dd5773db2d2c372f20:
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-updates-250521-2' into staging (2021-05-25 17:31:04 +0100)
are available in the Git repository at:
git://github.com/vivier/qemu-m68k.git tags/m68k-for-6.1-pull-request
for you to fetch changes up to 5e50c6c72bf8575f124ec9397411f4a2ff0d0206:
target/m68k: implement m68k "any instruction" trace mode (2021-05-26 20:45:18 +0200)
----------------------------------------------------------------
m68k pull request 20210526
implement m68k "any instruction" trace mode
----------------------------------------------------------------
Mark Cave-Ayland (4):
target/m68k: introduce is_singlestepping() function
target/m68k: call gen_raise_exception() directly if single-stepping in
gen_jmp_tb()
target/m68k: introduce gen_singlestep_exception() function
target/m68k: implement m68k "any instruction" trace mode
target/m68k/cpu.h | 8 +++++++
target/m68k/translate.c | 51 ++++++++++++++++++++++++++++++++++-------
2 files changed, 51 insertions(+), 8 deletions(-)
--
2.31.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PULL 1/4] target/m68k: introduce is_singlestepping() function
2021-05-26 19:57 [PULL 0/4] M68k for 6.1 patches Laurent Vivier
@ 2021-05-26 19:57 ` Laurent Vivier
2021-05-26 19:57 ` [PULL 2/4] target/m68k: call gen_raise_exception() directly if single-stepping in gen_jmp_tb() Laurent Vivier
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Laurent Vivier @ 2021-05-26 19:57 UTC (permalink / raw
To: qemu-devel; +Cc: Richard Henderson, Mark Cave-Ayland, Laurent Vivier
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
The m68k translator currently checks the DisasContextBase singlestep_enabled
boolean directly to determine whether to single-step execution. Soon
single-stepping may also be triggered by setting the appropriate bits in the
SR register so centralise the check into a single is_singlestepping()
function.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210519142917.16693-2-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target/m68k/translate.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 200018ae6a63..c774f2e8f0fc 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -194,6 +194,17 @@ static void do_writebacks(DisasContext *s)
}
}
+static bool is_singlestepping(DisasContext *s)
+{
+ /*
+ * Return true if we are singlestepping either because of QEMU gdbstub
+ * singlestep. This does not include the command line '-singlestep' mode
+ * which is rather misnamed as it only means "one instruction per TB" and
+ * doesn't affect the code we generate.
+ */
+ return s->base.singlestep_enabled;
+}
+
/* is_jmp field values */
#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
#define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
@@ -1506,7 +1517,7 @@ static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
/* Generate a jump to an immediate address. */
static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
{
- if (unlikely(s->base.singlestep_enabled)) {
+ if (unlikely(is_singlestepping(s))) {
gen_exception(s, dest, EXCP_DEBUG);
} else if (use_goto_tb(s, dest)) {
tcg_gen_goto_tb(n);
@@ -6245,7 +6256,7 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
break;
case DISAS_TOO_MANY:
update_cc_op(dc);
- if (dc->base.singlestep_enabled) {
+ if (is_singlestepping(dc)) {
tcg_gen_movi_i32(QREG_PC, dc->pc);
gen_raise_exception(EXCP_DEBUG);
} else {
@@ -6254,7 +6265,7 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
break;
case DISAS_JUMP:
/* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
- if (dc->base.singlestep_enabled) {
+ if (is_singlestepping(dc)) {
gen_raise_exception(EXCP_DEBUG);
} else {
tcg_gen_lookup_and_goto_ptr();
@@ -6265,7 +6276,7 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
* We updated CC_OP and PC in gen_exit_tb, but also modified
* other state that may require returning to the main loop.
*/
- if (dc->base.singlestep_enabled) {
+ if (is_singlestepping(dc)) {
gen_raise_exception(EXCP_DEBUG);
} else {
tcg_gen_exit_tb(NULL, 0);
--
2.31.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PULL 2/4] target/m68k: call gen_raise_exception() directly if single-stepping in gen_jmp_tb()
2021-05-26 19:57 [PULL 0/4] M68k for 6.1 patches Laurent Vivier
2021-05-26 19:57 ` [PULL 1/4] target/m68k: introduce is_singlestepping() function Laurent Vivier
@ 2021-05-26 19:57 ` Laurent Vivier
2021-05-26 19:57 ` [PULL 3/4] target/m68k: introduce gen_singlestep_exception() function Laurent Vivier
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Laurent Vivier @ 2021-05-26 19:57 UTC (permalink / raw
To: qemu-devel; +Cc: Richard Henderson, Mark Cave-Ayland, Laurent Vivier
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
In order to consolidate the single-step exception handling into a single
helper, change gen_jmp_tb() so that it calls gen_raise_exception() directly
instead of gen_exception(). This ensures that all single-step exceptions are
now handled directly by gen_raise_exception().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210519142917.16693-3-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target/m68k/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index c774f2e8f0fc..f14ecab5a502 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -1518,7 +1518,9 @@ static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
{
if (unlikely(is_singlestepping(s))) {
- gen_exception(s, dest, EXCP_DEBUG);
+ update_cc_op(s);
+ tcg_gen_movi_i32(QREG_PC, dest);
+ gen_raise_exception(EXCP_DEBUG);
} else if (use_goto_tb(s, dest)) {
tcg_gen_goto_tb(n);
tcg_gen_movi_i32(QREG_PC, dest);
--
2.31.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PULL 3/4] target/m68k: introduce gen_singlestep_exception() function
2021-05-26 19:57 [PULL 0/4] M68k for 6.1 patches Laurent Vivier
2021-05-26 19:57 ` [PULL 1/4] target/m68k: introduce is_singlestepping() function Laurent Vivier
2021-05-26 19:57 ` [PULL 2/4] target/m68k: call gen_raise_exception() directly if single-stepping in gen_jmp_tb() Laurent Vivier
@ 2021-05-26 19:57 ` Laurent Vivier
2021-05-26 19:57 ` [PULL 4/4] target/m68k: implement m68k "any instruction" trace mode Laurent Vivier
2021-05-28 15:24 ` [PULL 0/4] M68k for 6.1 patches Peter Maydell
4 siblings, 0 replies; 6+ messages in thread
From: Laurent Vivier @ 2021-05-26 19:57 UTC (permalink / raw
To: qemu-devel; +Cc: Richard Henderson, Mark Cave-Ayland, Laurent Vivier
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Introduce a new gen_singlestep_exception() function to be called when generating
the EXCP_DEBUG exception in single-step mode rather than calling
gen_raise_exception(EXCP_DEBUG) directly. This allows for the single-step
exception behaviour for all callers to be managed in a single place.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210519142917.16693-4-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target/m68k/translate.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index f14ecab5a502..10e8aba42e42 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -319,6 +319,15 @@ static void gen_exception(DisasContext *s, uint32_t dest, int nr)
s->base.is_jmp = DISAS_NORETURN;
}
+static void gen_singlestep_exception(DisasContext *s)
+{
+ /*
+ * Generate the right kind of exception for singlestep, which is
+ * EXCP_DEBUG for QEMU's gdb singlestepping.
+ */
+ gen_raise_exception(EXCP_DEBUG);
+}
+
static inline void gen_addr_fault(DisasContext *s)
{
gen_exception(s, s->base.pc_next, EXCP_ADDRESS);
@@ -1520,7 +1529,7 @@ static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
if (unlikely(is_singlestepping(s))) {
update_cc_op(s);
tcg_gen_movi_i32(QREG_PC, dest);
- gen_raise_exception(EXCP_DEBUG);
+ gen_singlestep_exception(s);
} else if (use_goto_tb(s, dest)) {
tcg_gen_goto_tb(n);
tcg_gen_movi_i32(QREG_PC, dest);
@@ -6260,7 +6269,7 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
update_cc_op(dc);
if (is_singlestepping(dc)) {
tcg_gen_movi_i32(QREG_PC, dc->pc);
- gen_raise_exception(EXCP_DEBUG);
+ gen_singlestep_exception(dc);
} else {
gen_jmp_tb(dc, 0, dc->pc);
}
@@ -6268,7 +6277,7 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
case DISAS_JUMP:
/* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
if (is_singlestepping(dc)) {
- gen_raise_exception(EXCP_DEBUG);
+ gen_singlestep_exception(dc);
} else {
tcg_gen_lookup_and_goto_ptr();
}
@@ -6279,7 +6288,7 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
* other state that may require returning to the main loop.
*/
if (is_singlestepping(dc)) {
- gen_raise_exception(EXCP_DEBUG);
+ gen_singlestep_exception(dc);
} else {
tcg_gen_exit_tb(NULL, 0);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PULL 4/4] target/m68k: implement m68k "any instruction" trace mode
2021-05-26 19:57 [PULL 0/4] M68k for 6.1 patches Laurent Vivier
` (2 preceding siblings ...)
2021-05-26 19:57 ` [PULL 3/4] target/m68k: introduce gen_singlestep_exception() function Laurent Vivier
@ 2021-05-26 19:57 ` Laurent Vivier
2021-05-28 15:24 ` [PULL 0/4] M68k for 6.1 patches Peter Maydell
4 siblings, 0 replies; 6+ messages in thread
From: Laurent Vivier @ 2021-05-26 19:57 UTC (permalink / raw
To: qemu-devel; +Cc: Richard Henderson, Mark Cave-Ayland, Laurent Vivier
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
The m68k trace mode is controlled by the top 2 bits in the SR register. Implement
the m68k "any instruction" trace mode where bit T1=1 and bit T0=0 in which the CPU
generates an EXCP_TRACE exception (vector 9 or offset 0x24) after executing each
instruction.
This functionality is used by the NetBSD kernel debugger to allow single-stepping
on m68k architectures.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210519142917.16693-5-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target/m68k/cpu.h | 8 ++++++++
target/m68k/translate.c | 27 ++++++++++++++++++++-------
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 402c86c8769e..997d588911c6 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -230,6 +230,9 @@ typedef enum {
#define SR_T_SHIFT 14
#define SR_T 0xc000
+#define M68K_SR_TRACE(sr) ((sr & SR_T) >> SR_T_SHIFT)
+#define M68K_SR_TRACE_ANY_INS 0x2
+
#define M68K_SSP 0
#define M68K_USP 1
#define M68K_ISP 2
@@ -590,6 +593,8 @@ typedef M68kCPU ArchCPU;
#define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT)
#define TB_FLAGS_DFC_S_BIT 15
#define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT)
+#define TB_FLAGS_TRACE 16
+#define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE)
static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
@@ -602,6 +607,9 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
*flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
*flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
}
+ if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) {
+ *flags |= TB_FLAGS_TRACE;
+ }
}
void dump_mmu(CPUM68KState *env);
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 10e8aba42e42..f0c5bf9154e0 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -124,6 +124,7 @@ typedef struct DisasContext {
#define MAX_TO_RELEASE 8
int release_count;
TCGv release[MAX_TO_RELEASE];
+ bool ss_active;
} DisasContext;
static void init_release_array(DisasContext *s)
@@ -197,12 +198,13 @@ static void do_writebacks(DisasContext *s)
static bool is_singlestepping(DisasContext *s)
{
/*
- * Return true if we are singlestepping either because of QEMU gdbstub
- * singlestep. This does not include the command line '-singlestep' mode
- * which is rather misnamed as it only means "one instruction per TB" and
- * doesn't affect the code we generate.
+ * Return true if we are singlestepping either because of
+ * architectural singlestep or QEMU gdbstub singlestep. This does
+ * not include the command line '-singlestep' mode which is rather
+ * misnamed as it only means "one instruction per TB" and doesn't
+ * affect the code we generate.
*/
- return s->base.singlestep_enabled;
+ return s->base.singlestep_enabled || s->ss_active;
}
/* is_jmp field values */
@@ -323,9 +325,14 @@ static void gen_singlestep_exception(DisasContext *s)
{
/*
* Generate the right kind of exception for singlestep, which is
- * EXCP_DEBUG for QEMU's gdb singlestepping.
+ * either the architectural singlestep or EXCP_DEBUG for QEMU's
+ * gdb singlestepping.
*/
- gen_raise_exception(EXCP_DEBUG);
+ if (s->ss_active) {
+ gen_raise_exception(EXCP_TRACE);
+ } else {
+ gen_raise_exception(EXCP_DEBUG);
+ }
}
static inline void gen_addr_fault(DisasContext *s)
@@ -6194,6 +6201,12 @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
dc->done_mac = 0;
dc->writeback_mask = 0;
init_release_array(dc);
+
+ dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS);
+ /* If architectural single step active, limit to 1 */
+ if (is_singlestepping(dc)) {
+ dc->base.max_insns = 1;
+ }
}
static void m68k_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
--
2.31.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PULL 0/4] M68k for 6.1 patches
2021-05-26 19:57 [PULL 0/4] M68k for 6.1 patches Laurent Vivier
` (3 preceding siblings ...)
2021-05-26 19:57 ` [PULL 4/4] target/m68k: implement m68k "any instruction" trace mode Laurent Vivier
@ 2021-05-28 15:24 ` Peter Maydell
4 siblings, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2021-05-28 15:24 UTC (permalink / raw
To: Laurent Vivier; +Cc: QEMU Developers
On Wed, 26 May 2021 at 21:15, Laurent Vivier <laurent@vivier.eu> wrote:
>
> The following changes since commit 0319ad22bd5789e1eaa8a2dd5773db2d2c372f20:
>
> Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-updates-250521-2' into staging (2021-05-25 17:31:04 +0100)
>
> are available in the Git repository at:
>
> git://github.com/vivier/qemu-m68k.git tags/m68k-for-6.1-pull-request
>
> for you to fetch changes up to 5e50c6c72bf8575f124ec9397411f4a2ff0d0206:
>
> target/m68k: implement m68k "any instruction" trace mode (2021-05-26 20:45:18 +0200)
>
> ----------------------------------------------------------------
> m68k pull request 20210526
>
> implement m68k "any instruction" trace mode
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread
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2021-05-26 19:57 [PULL 0/4] M68k for 6.1 patches Laurent Vivier
2021-05-26 19:57 ` [PULL 1/4] target/m68k: introduce is_singlestepping() function Laurent Vivier
2021-05-26 19:57 ` [PULL 2/4] target/m68k: call gen_raise_exception() directly if single-stepping in gen_jmp_tb() Laurent Vivier
2021-05-26 19:57 ` [PULL 3/4] target/m68k: introduce gen_singlestep_exception() function Laurent Vivier
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