From: Chris Browy <cbrowy@avery-design.com>
To: mst@redhat.com
Cc: ben.widawsky@intel.com, david@redhat.com, qemu-devel@nongnu.org,
vishal.l.verma@intel.com, jgroves@micron.com,
Chris Browy <cbrowy@avery-design.com>,
armbru@redhat.com, f4bug@amsat.org, hchkuo@avery-design.com.tw,
tyshao@avery-design.com.tw, jonathan.cameron@huawei.com,
imammedo@redhat.com, dan.j.williams@intel.com,
ira.weiny@intel.com
Subject: [PATCH v6 cxl2.0-v6-doe 2/6] include/hw/pci: headers for PCIe DOE
Date: Thu, 10 Jun 2021 09:15:57 -0400 [thread overview]
Message-ID: <1623330957-18354-1-git-send-email-cbrowy@avery-design.com> (raw)
In-Reply-To: <1623329999-15662-1-git-send-email-cbrowy@avery-design.com>
From: hchkuo <hchkuo@avery-design.com.tw>
Macros for the vender ID of PCI-SIG mentioned in "PCIe Data Object
Exchange ECN, March 12, 2020" and the size of PCIe Data Object
Exchange.
Signed-off-by: hchkuo <hchkuo@avery-design.com.tw>
Signed-off-by: Chris Browy <cbrowy@avery-design.com>
---
include/hw/pci/pci_ids.h | 3 +++
include/hw/pci/pcie_regs.h | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h
index 95f92d98e9..2656009cfe 100644
--- a/include/hw/pci/pci_ids.h
+++ b/include/hw/pci/pci_ids.h
@@ -157,6 +157,9 @@
/* Vendors and devices. Sort key: vendor first, device next. */
+/* Ref: PCIe Data Object Exchange ECN, March 12, 2020, Table 7-x2 */
+#define PCI_VENDOR_ID_PCI_SIG 0x0001
+
#define PCI_VENDOR_ID_LSI_LOGIC 0x1000
#define PCI_DEVICE_ID_LSI_53C810 0x0001
#define PCI_DEVICE_ID_LSI_53C895A 0x0012
diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h
index 1db86b0ec4..963dc2e170 100644
--- a/include/hw/pci/pcie_regs.h
+++ b/include/hw/pci/pcie_regs.h
@@ -179,4 +179,8 @@ typedef enum PCIExpLinkWidth {
#define PCI_ACS_VER 0x1
#define PCI_ACS_SIZEOF 8
+/* DOE Capability Register Fields */
+#define PCI_DOE_VER 0x1
+#define PCI_DOE_SIZEOF 24
+
#endif /* QEMU_PCIE_REGS_H */
--
2.17.1
next prev parent reply other threads:[~2021-06-10 13:18 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-10 12:59 [PATCH v6 cxl2.0-v6-doe 0/6] QEMU PCIe DOE for PCIe 4.0/5.0 and CXL 2.0 Chris Browy
2021-06-10 13:15 ` [PATCH v6 cxl2.0-v6-doe 1/6] standard-headers/linux/pci_regs: PCI header from Linux kernel Chris Browy
2021-06-15 17:42 ` Jonathan Cameron
2021-06-15 18:46 ` Michael S. Tsirkin
2021-06-10 13:15 ` Chris Browy [this message]
2021-06-15 17:40 ` [PATCH v6 cxl2.0-v6-doe 2/6] include/hw/pci: headers for PCIe DOE Jonathan Cameron
2021-06-10 13:16 ` [PATCH v6 cxl2.0-v6-doe 3/6] hw/pci: PCIe Data Object Exchange implementation Chris Browy
2021-06-15 18:21 ` Jonathan Cameron
2021-07-02 15:02 ` Michael S. Tsirkin
2021-06-10 13:16 ` [PATCH v6 cxl2.0-v6-doe 4/6] cxl/compliance: CXL Compliance " Chris Browy
2021-06-15 21:10 ` Jonathan Cameron
2021-06-10 13:16 ` [PATCH v6 cxl2.0-v6-doe 5/6] cxl/cdat: CXL CDAT " Chris Browy
2021-06-16 9:52 ` Jonathan Cameron
2021-06-10 13:16 ` [PATCH v6 cxl2.0-v6-doe 6/6] test/cdat: CXL CDAT test data Chris Browy
2021-06-16 10:44 ` Jonathan Cameron
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