From: Hao Lee <haolee.swjtu@gmail.com>
To: paulmck@kernel.org
Cc: perfbook@vger.kernel.org
Subject: Clarify what the read memory barrier really does
Date: Sun, 17 Apr 2022 11:17:26 +0000 [thread overview]
Message-ID: <20220417111726.GA27498@haolee.io> (raw)
Hello,
I think maybe we can make the following contents more clear:
Cite from Appendix C.4:
when a given CPU executes a memory barrier, it marks all the
entries currently in its invalidate queue, and forces any
subsequent load to wait until all marked entries have been
applied to the CPU’s cache.
It's obvious that this paragraph means read barrier can flush invalidate
queue.
Cite from Appendix C.5:
The effect of this is that a read memory barrier orders only
loads on the CPU that executes it, so that all loads preceding
the read memory barrier will appear to have completed before any
load following the read memory barrier.
This paragraph means read barrier can prevent Load-Load memory
reordering which is caused by out-of-order execution.
If I understand correctly, read memory barrier has _two functions_, one
is flushing invalidate queue to make the loads following the barrier can
load the latest value, and the other is stalling instruction pipeline to
prevent Load-Load memory reordering. I think these are two completely
different functions and we should make such a summary in the book.
Regards,
Hao Lee
next reply other threads:[~2022-04-17 11:17 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-17 11:17 Hao Lee [this message]
2022-04-17 17:34 ` Clarify what the read memory barrier really does Paul E. McKenney
2022-04-18 7:37 ` Hao Lee
2022-04-19 17:31 ` Paul E. McKenney
2022-04-20 6:57 ` Hao Lee
2022-04-21 3:58 ` Paul E. McKenney
2022-04-21 13:37 ` Hao Lee
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