From: Hao Lee <haolee.swjtu@gmail.com>
To: paulmck@kernel.org
Cc: perfbook@vger.kernel.org, haolee.swjtu@gmail.com
Subject: [PATCH] whymb: fix description in DMA coherence
Date: Sun, 17 Apr 2022 11:09:47 +0000 [thread overview]
Message-ID: <20220417110947.GA27447@haolee.io> (raw)
CPU caches need to be flushed before DMA operations to avoid data
overwriting.
Signed-off-by: Hao Lee <haolee.swjtu@gmail.com>
---
appendix/whymb/whymemorybarriers.tex | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/appendix/whymb/whymemorybarriers.tex b/appendix/whymb/whymemorybarriers.tex
index b49d5fe8..4ec27962 100644
--- a/appendix/whymb/whymemorybarriers.tex
+++ b/appendix/whymb/whymemorybarriers.tex
@@ -1640,7 +1640,7 @@ future such problems:
in any DMA buffer before presenting that buffer to the
I/O device.
Similarly, you need to flush the CPU caches of any location
- in any DMA buffer after DMA to that buffer completes.
+ in any DMA buffer before DMA to that buffer completes.
And even then, you need to be \emph{very} careful to avoid
pointer bugs, as even a misplaced read to an input buffer
can result in corrupting the data input!
--
2.21.0
next reply other threads:[~2022-04-17 11:09 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-17 11:09 Hao Lee [this message]
2022-04-17 16:52 ` [PATCH] whymb: fix description in DMA coherence Paul E. McKenney
2022-04-18 6:23 ` Hao Lee
2022-04-19 17:36 ` Paul E. McKenney
2022-04-20 11:38 ` Hao Lee
2022-04-29 15:43 ` Hao Lee
2022-04-29 17:40 ` Paul E. McKenney
2022-04-30 14:18 ` Hao Lee
2022-04-30 14:56 ` Paul E. McKenney
2022-05-06 19:51 ` Paul E. McKenney
2022-05-07 16:59 ` Hao Lee
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