From: Robert Finch <robfi680@gmail.com>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] Tomasulo's Core
Date: Sun, 10 Apr 2022 21:01:56 -0400 [thread overview]
Message-ID: <CAOkYDM+3gwtprv87SzZaiZ+bkhe5Vc3SZ-txTzrxjR_9SHKW9Q@mail.gmail.com> (raw)
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Hi, I have been perusing the OpenRISC site and studying the OpenRISC
design. I read a comment about the lack of out-of-order cores and thought
people may be interested in the one I am working on. It is not really ready
for prime-time yet. It is located in Github at
https://github.com/robfinch/Thor/tree/main/Thor2022
It is another core using a version of Tomasulo’s Algorithm.
I was glad to see the OpenRISC design make branch delay slots optional. Is
there a way to set a true/ false value in a register using a set
instruction? OpenRISC looks like an excellent design. I am interested in
64/128 bit though. 128-bit decimal floating-point.
Robert Finch
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next reply other threads:[~2022-04-11 1:01 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-11 1:01 Robert Finch [this message]
2022-04-13 20:48 ` [OpenRISC] Tomasulo's Core Stafford Horne
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