From: Tomer Maimon <tmaimon77@gmail.com>
To: Stephen Boyd <sboyd@kernel.org>
Cc: benjaminfair@google.com, avifishman70@gmail.com,
venture@google.com, mturquette@baylibre.com,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
tali.perry1@gmail.com, joel@jms.id.au, openbmc@lists.ozlabs.org
Subject: Re: [PATCH RESEND v21] clk: npcm8xx: add clock controller
Date: Wed, 3 Jan 2024 13:14:35 +0200 [thread overview]
Message-ID: <CAP6Zq1hTGWcG+63QV2rUVw92E51_NdoXCQaKTCrWNkJDGiEXwQ@mail.gmail.com> (raw)
In-Reply-To: <5b31aa5cfb1e819b03678d080b630667.sboyd@kernel.org>
Hi Stephen,
Thanks for your clarifications.
On Wed, 3 Jan 2024 at 01:52, Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Tomer Maimon (2023-12-21 05:43:20)
> > Hi Stephen,
> >
> > Thanks for your comments
> >
> > On Thu, 21 Dec 2023 at 00:09, Stephen Boyd <sboyd@kernel.org> wrote:
> > >
> > > Quoting Tomer Maimon (2023-12-18 09:04:04)
> > > > diff --git a/drivers/clk/clk-npcm8xx.c b/drivers/clk/clk-npcm8xx.c
> > > > new file mode 100644
> > > > index 000000000000..e6c5111cc255
> > > > --- /dev/null
> > > > +++ b/drivers/clk/clk-npcm8xx.c
> > > > @@ -0,0 +1,552 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/*
> > > > + * Nuvoton NPCM8xx Clock Generator
> > > > + * All the clocks are initialized by the bootloader, so this driver allows only
> > > > + * reading of current settings directly from the hardware.
> > > > + *
> > > > + * Copyright (C) 2020 Nuvoton Technologies
> > > > + * Author: Tomer Maimon <tomer.maimon@nuvoton.com>
> > > > + */
> > > > +
> > > > +#define pr_fmt(fmt) "npcm8xx_clk: " fmt
> > > > +
> > > > +#include <linux/bitfield.h>
> > > > +#include <linux/clk-provider.h>
> > > > +#include <linux/err.h>
> > > > +#include <linux/io.h>
> > > > +#include <linux/kernel.h>
> > > > +#include <linux/module.h>
> > > > +#include <linux/platform_device.h>
> > > > +#include <linux/slab.h>
> > > > +#include <linux/regmap.h>
> > > [...]
> > > > +#define NPCM8XX_CLK_S_CLKOUT "clkout"
> > > > +#define NPCM8XX_CLK_S_PRE_ADC "pre adc"
> > > > +#define NPCM8XX_CLK_S_UART "uart"
> > > > +#define NPCM8XX_CLK_S_UART2 "uart2"
> > > > +#define NPCM8XX_CLK_S_TIMER "timer"
> > > > +#define NPCM8XX_CLK_S_MMC "mmc"
> > > > +#define NPCM8XX_CLK_S_SDHC "sdhc"
> > > > +#define NPCM8XX_CLK_S_ADC "adc"
> > > > +#define NPCM8XX_CLK_S_GFX "gfx0_gfx1_mem"
> > > > +#define NPCM8XX_CLK_S_USBIF "serial_usbif"
> > > > +#define NPCM8XX_CLK_S_USB_HOST "usb_host"
> > > > +#define NPCM8XX_CLK_S_USB_BRIDGE "usb_bridge"
> > > > +#define NPCM8XX_CLK_S_PCI "pci"
> > > > +#define NPCM8XX_CLK_S_TH "th"
> > > > +#define NPCM8XX_CLK_S_ATB "atb"
> > > > +#define NPCM8XX_CLK_S_PRE_CLK "pre_clk"
> > > > +#define NPCM8XX_CLK_S_RG "rg"
> > > > +#define NPCM8XX_CLK_S_RCP "rcp"
> > > > +
> > > > +static struct clk_hw hw_pll1_div2, hw_pll2_div2, hw_gfx_div2, hw_pre_clk;
> > > > +static struct npcm8xx_clk_pll_data npcm8xx_pll_clks[] = {
> > > > + { NPCM8XX_CLK_S_PLL0, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCON0, 0 },
> > >
> > > This is a new driver, so please stop using .name in clk_parent_data
> > > structures.
> > A few versions ago you suggested defining the reference clock in the
> > device tree,Can I use .fw_name since the reference clock in the device
> > tree
> >
> > refclk: refclk-25mhz {
> > compatible = "fixed-clock";
> > clock-output-names = "refclk";
>
> Please don't use clock-output-names property.
Will remove
>
> > clock-frequency = <25000000>;
> > #clock-cells = <0>;
> > };
>
> Use of this binding is fine assuming the reference clk is a real thing
> that exists outside the SoC. Is it?
Yes it is.
>
> >
> > clk: clock-controller@f0801000 {
> > compatible = "nuvoton,npcm845-clk";
> > nuvoton,sysclk = <&rst>;
> > #clock-cells = <1>;
> > clocks = <&refclk>;
>
> This is index = 0
O.K.
>
> > clock-names = "refclk";
> > };
> >
> > I will make sure to add refclk-25mhz to NPCM8xx device tree.
> > >
> > > > + { NPCM8XX_CLK_S_PLL1, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCON1, 0 },
> > > > + { NPCM8XX_CLK_S_PLL2, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCON2, 0 },
> > > > + { NPCM8XX_CLK_S_PLL_GFX, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCONG, 0 },
> > > > +};
> > > > +
> > > > +static const u32 cpuck_mux_table[] = { 0, 1, 2, 7 };
> > > > +static const struct clk_parent_data cpuck_mux_parents[] = {
> > > > + { .hw = &npcm8xx_pll_clks[0].hw },
> > > > + { .hw = &npcm8xx_pll_clks[1].hw },
> > > > + { .index = 0 },
> > >
> > > This requires a binding update. As of today, there isn't a 'clocks'
> > > property for the nuvoton,npcm845-clk binding.
> > Can I use fw_name = NPCM8XX_CLK_S_REFCLK instead of .index = 0 in
> > that way, I will not need to modify nuvoton,npcm845-clk binding.
>
> Why don't you want to modify the binding? If you add a clocks property
> like in the example above you will have to modify the binding.
Will add clocks property to nuvoton,npcm845-clk binding.
Thanks,
Tomer
prev parent reply other threads:[~2024-01-03 11:15 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-18 17:04 [PATCH RESEND v21] clk: npcm8xx: add clock controller Tomer Maimon
2023-12-20 22:09 ` Stephen Boyd
2023-12-21 13:43 ` Tomer Maimon
2024-01-02 23:52 ` Stephen Boyd
2024-01-03 11:14 ` Tomer Maimon [this message]
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