From: Iwona Winiarska <iwona.winiarska@intel.com>
To: openbmc@lists.ozlabs.org, linux-kernel@vger.kernel.org,
linux-aspeed@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org
Cc: Billy Tsai <billy_tsai@aspeedtech.com>,
Iwona Winiarska <iwona.winiarska@intel.com>
Subject: [PATCH] peci: aspeed: Clear clock_divider value before setting it
Date: Wed, 17 Apr 2024 15:48:49 +0200 [thread overview]
Message-ID: <20240417134849.5793-1-iwona.winiarska@intel.com> (raw)
PECI clock divider is programmed on 10:8 bits of PECI Control register.
Before setting a new value, clear bits read from hardware.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
---
drivers/peci/controller/peci-aspeed.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/peci/controller/peci-aspeed.c b/drivers/peci/controller/peci-aspeed.c
index 7fdc25afcf2f..de7046e6b9c4 100644
--- a/drivers/peci/controller/peci-aspeed.c
+++ b/drivers/peci/controller/peci-aspeed.c
@@ -351,6 +351,7 @@ static int clk_aspeed_peci_set_rate(struct clk_hw *hw, unsigned long rate,
clk_aspeed_peci_find_div_values(this_rate, &msg_timing, &clk_div_exp);
val = readl(aspeed_peci->base + ASPEED_PECI_CTRL);
+ val &= ~ASPEED_PECI_CTRL_CLK_DIV_MASK;
val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, clk_div_exp);
writel(val, aspeed_peci->base + ASPEED_PECI_CTRL);
--
2.44.0
next reply other threads:[~2024-04-17 13:50 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-17 13:48 Iwona Winiarska [this message]
2024-04-17 23:41 ` [PATCH] peci: aspeed: Clear clock_divider value before setting it Andrew Jeffery
2024-04-18 13:41 ` Winiarska, Iwona
2024-04-18 23:25 ` Andrew Jeffery
2024-06-12 2:23 ` Billy Tsai
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