From: kernel test robot <lkp@intel.com>
To: Alex Deucher <alexander.deucher@amd.com>
Cc: oe-kbuild-all@lists.linux.dev,
Linux Memory Management List <linux-mm@kvack.org>
Subject: [linux-next:master 12913/12990] drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn35/dcn35_optc.c:59: warning: Function parameter or struct member 'segment_width' not described in 'optc35_set_odm_combine'
Date: Tue, 14 May 2024 18:44:45 +0800 [thread overview]
Message-ID: <202405141810.w4NzVd8m-lkp@intel.com> (raw)
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head: 26dd54d03cd94ecc035d9e1e9fd4fc0f3ab311cf
commit: cbc3288064a9198d81cb3b827d3adfa4a4a0b813 [12913/12990] Merge branch 'drm-next' of https://gitlab.freedesktop.org/agd5f/linux
config: powerpc-randconfig-m041-20220831 (https://download.01.org/0day-ci/archive/20240514/202405141810.w4NzVd8m-lkp@intel.com/config)
compiler: powerpc-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240514/202405141810.w4NzVd8m-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202405141810.w4NzVd8m-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn35/dcn35_optc.c:59: warning: Function parameter or struct member 'segment_width' not described in 'optc35_set_odm_combine'
>> drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn35/dcn35_optc.c:59: warning: Function parameter or struct member 'last_segment_width' not described in 'optc35_set_odm_combine'
>> drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn35/dcn35_optc.c:59: warning: Excess function parameter 'timing' description in 'optc35_set_odm_combine'
vim +59 drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn35/dcn35_optc.c
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 36
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 37 #define REG(reg)\
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 38 optc1->tg_regs->reg
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 39
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 40 #define CTX \
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 41 optc1->base.ctx
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 42
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 43 #undef FN
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 44 #define FN(reg_name, field_name) \
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 45 optc1->tg_shift->field_name, optc1->tg_mask->field_name
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 46
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 47 /**
eae369917516ff drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Srinivasan Shanmugam 2023-08-29 48 * optc35_set_odm_combine() - Enable CRTC - call ASIC Control Object to enable Timing generator.
eae369917516ff drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Srinivasan Shanmugam 2023-08-29 49 *
eae369917516ff drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Srinivasan Shanmugam 2023-08-29 50 * @optc: Output Pipe Timing Combine instance reference.
eae369917516ff drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Srinivasan Shanmugam 2023-08-29 51 * @opp_id: Output Plane Processor instance ID.
eae369917516ff drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Srinivasan Shanmugam 2023-08-29 52 * @opp_cnt: Output Plane Processor count.
eae369917516ff drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Srinivasan Shanmugam 2023-08-29 53 * @timing: Timing parameters used to configure DCN blocks.
eae369917516ff drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Srinivasan Shanmugam 2023-08-29 54 *
eae369917516ff drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Srinivasan Shanmugam 2023-08-29 55 * Return: void.
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 56 */
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 57 static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
f9d48a88eba547 drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c Wenjing Liu 2024-04-25 58 int segment_width, int last_segment_width)
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 @59 {
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 60 struct optc *optc1 = DCN10TG_FROM_TG(optc);
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 61 uint32_t memory_mask = 0;
f9d48a88eba547 drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c Wenjing Liu 2024-04-25 62 int h_active = segment_width * opp_cnt;
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 63 /* Each memory instance is 2048x(314x2) bits to support half line of 4096 */
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 64 int odm_mem_count = (h_active + 2047) / 2048;
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 65
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 66 /*
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 67 * display <= 4k : 2 memories + 2 pipes
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 68 * 4k < display <= 8k : 4 memories + 2 pipes
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 69 * 8k < display <= 12k : 6 memories + 4 pipes
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 70 */
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 71 if (opp_cnt == 4) {
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 72 if (odm_mem_count <= 2)
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 73 memory_mask = 0x3;
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 74 else if (odm_mem_count <= 4)
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 75 memory_mask = 0xf;
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 76 else
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 77 memory_mask = 0x3f;
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 78 } else {
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 79 if (odm_mem_count <= 2)
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 80 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 81 else if (odm_mem_count <= 4)
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 82 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 83 else
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 84 memory_mask = 0x77;
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 85 }
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 86
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 87 REG_SET(OPTC_MEMORY_CONFIG, 0,
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 88 OPTC_MEM_SEL, memory_mask);
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 89
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 90 if (opp_cnt == 2) {
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 91 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 92 OPTC_NUM_OF_INPUT_SEGMENT, 1,
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 93 OPTC_SEG0_SRC_SEL, opp_id[0],
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 94 OPTC_SEG1_SRC_SEL, opp_id[1]);
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 95 } else if (opp_cnt == 4) {
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 96 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 97 OPTC_NUM_OF_INPUT_SEGMENT, 3,
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 98 OPTC_SEG0_SRC_SEL, opp_id[0],
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 99 OPTC_SEG1_SRC_SEL, opp_id[1],
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 100 OPTC_SEG2_SRC_SEL, opp_id[2],
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 101 OPTC_SEG3_SRC_SEL, opp_id[3]);
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 102 }
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 103
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 104 REG_UPDATE(OPTC_WIDTH_CONTROL,
f9d48a88eba547 drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c Wenjing Liu 2024-04-25 105 OPTC_SEGMENT_WIDTH, segment_width);
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 106
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 107 REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 108 optc1->opp_count = opp_cnt;
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 109 }
b9c96af677cbed drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c Qingqing Zhuo 2023-08-03 110
:::::: The code at line 59 was first introduced by commit
:::::: b9c96af677cbed62c07272594312cc8198293a24 drm/amd/display: Add DCN35 OPTC
:::::: TO: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
:::::: CC: Alex Deucher <alexander.deucher@amd.com>
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
reply other threads:[~2024-05-14 10:45 UTC|newest]
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