From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Lukas Wunner <lukas@wunner.de>
Cc: "open list:THUNDERBOLT DRIVER" <linux-usb@vger.kernel.org>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS"
<nouveau@lists.freedesktop.org>,
"open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS"
<dri-devel@lists.freedesktop.org>,
"open list:X86 PLATFORM DRIVERS"
<platform-driver-x86@vger.kernel.org>,
"Mario Limonciello" <mario.limonciello@amd.com>,
"Andreas Noever" <andreas.noever@gmail.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Marek Behún" <kabel@kernel.org>,
"open list:RADEON and AMDGPU DRM DRIVERS"
<amd-gfx@lists.freedesktop.org>,
"open list:ACPI" <linux-acpi@vger.kernel.org>,
"open list:PCI SUBSYSTEM" <linux-pci@vger.kernel.org>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Michael Jamet" <michael.jamet@intel.com>,
"Mark Gross" <markgross@kernel.org>,
"Hans de Goede" <hdegoede@redhat.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Xinhui Pan" <Xinhui.Pan@amd.com>,
"open list" <linux-kernel@vger.kernel.org>,
"Daniel Vetter" <daniel@ffwll.ch>,
"Yehezkel Bernat" <YehezkelShB@gmail.com>,
"Pali Rohár" <pali@kernel.org>,
"Christian König" <christian.koenig@amd.com>,
"Maciej W . Rozycki" <macro@orcam.me.uk>
Subject: Re: [Nouveau] [PATCH v2 8/9] PCI: Exclude PCIe ports used for tunneling in pcie_bandwidth_available()
Date: Tue, 7 Nov 2023 08:24:05 +0200 [thread overview]
Message-ID: <20231107062405.GU17433@black.fi.intel.com> (raw)
In-Reply-To: <20231107054526.GT17433@black.fi.intel.com>
On Tue, Nov 07, 2023 at 07:45:26AM +0200, Mika Westerberg wrote:
> Hi,
>
> On Mon, Nov 06, 2023 at 07:56:52PM +0100, Lukas Wunner wrote:
> > On Mon, Nov 06, 2023 at 12:44:25PM -0600, Mario Limonciello wrote:
> > > Tangentially related; the link speed is currently symmetric but there are
> > > two sysfs files. Mika left a comment in drivers/thunderbolt/switch.c it may
> > > be asymmetric in the future. So we may need to keep that in mind on any
> > > design that builds on top of them.
> >
> > Aren't asymmetric Thunderbolt speeds just a DisplayPort thing?
>
> No, they affect the whole fabric. We have the initial code for
> asymmetric switching in v6.7-rc1.
>
> > > As 'thunderbolt' can be a module or built in, we need to bring code into PCI
> > > core so that it works in early boot before it loads.
> >
> > tb_switch_get_generation() is small enough that it could be moved to the
> > PCI core. I doubt that we need to make thunderbolt built-in only
> > or move a large amount of code to the PCI core.
>
> If at all possible I would like to avoid this and littering PCI side
> with non-PCI stuff. There could be other similar "mediums" in the future
> where you can transfer packets of "native" protocols such as PCIe so
> instead of making it Thunderbolt/USB4 specific it should be generic
> enough to support future extensions.
>
> In case of Thunderbolt/USB4 there is no real way to figure out how much
> bandwidth each PCIe tunnel gets (it is kind of bulk traffic that gets
> what is left from isochronous protocols) so I would not even try that
> and instead use the real PCIe links in pcie_bandwidth_available() and
> skip all the "virtual" ones.
Actually can we call the new function something like pci_link_is_virtual()
instead and make pcie_bandwidth_available() call it? That would be more
future proof IMHO.
next prev parent reply other threads:[~2023-11-07 6:24 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-03 19:07 [Nouveau] [PATCH v2 0/9] Improvements to pcie_bandwidth_available() for eGPUs Mario Limonciello
2023-11-03 19:07 ` [Nouveau] [PATCH v2 1/9] drm/nouveau: Switch from pci_is_thunderbolt_attached() to dev_is_removable() Mario Limonciello
2023-11-06 12:25 ` Ilpo Järvinen
2023-11-06 16:47 ` [Nouveau] " Mika Westerberg
2023-11-06 16:49 ` Mario Limonciello
2023-11-03 19:07 ` [Nouveau] [PATCH v2 2/9] drm/radeon: " Mario Limonciello
2023-11-06 12:27 ` Ilpo Järvinen
2023-11-03 19:07 ` [Nouveau] [PATCH v2 3/9] PCI: Drop pci_is_thunderbolt_attached() Mario Limonciello
2023-11-06 12:33 ` Ilpo Järvinen
2023-11-06 16:46 ` [Nouveau] " Mario Limonciello
2023-11-03 19:07 ` [Nouveau] [PATCH v2 4/9] PCI: Move the `PCI_CLASS_SERIAL_USB_USB4` definition to common header Mario Limonciello
2023-11-03 19:07 ` [Nouveau] [PATCH v2 5/9] PCI: pciehp: Move check for is_thunderbolt into a quirk Mario Limonciello
2023-11-06 12:41 ` Ilpo Järvinen
2023-11-06 16:50 ` [Nouveau] " Mario Limonciello
2023-11-03 19:07 ` [Nouveau] [PATCH v2 6/9] PCI: Rename is_thunderbolt to is_tunneled Mario Limonciello
2023-11-03 19:38 ` Hans de Goede
2023-11-05 17:39 ` Lukas Wunner
2023-11-06 16:59 ` Mario Limonciello
2023-11-06 18:18 ` Lukas Wunner
2023-11-03 19:07 ` [Nouveau] [PATCH v2 7/9] PCI: ACPI: Detect PCIe root ports that are used for tunneling Mario Limonciello
2023-11-03 19:07 ` [Nouveau] [PATCH v2 8/9] PCI: Exclude PCIe ports used for tunneling in pcie_bandwidth_available() Mario Limonciello
2023-11-04 6:57 ` Lazar, Lijo
2023-11-06 12:52 ` Ilpo Järvinen
2023-11-06 16:51 ` [Nouveau] " Mario Limonciello
2023-11-06 18:10 ` Lukas Wunner
2023-11-06 18:44 ` Mario Limonciello
2023-11-06 18:56 ` Lukas Wunner
2023-11-07 5:45 ` Mika Westerberg
2023-11-07 6:24 ` Mika Westerberg [this message]
2023-11-03 19:07 ` [Nouveau] [PATCH v2 9/9] PCI: Add a quirk to mark 0x8086 : 0x9a23 as supporting PCIe tunneling Mario Limonciello
2023-11-03 19:20 ` [Nouveau] [PATCH v2 0/9] Improvements to pcie_bandwidth_available() for eGPUs Bjorn Helgaas
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