* [PATCH v1 0/8] Add Loongson-2k0500 and Loongson-2k2000 clock support
@ 2024-03-26 9:00 Binbin Zhou
2024-03-26 9:01 ` [PATCH v1 1/8] dt-bindings: clock: add Loongson-2K expand clock index Binbin Zhou
` (7 more replies)
0 siblings, 8 replies; 14+ messages in thread
From: Binbin Zhou @ 2024-03-26 9:00 UTC (permalink / raw
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou
Hi all:
As we know, the Loongson-2K family of SoCs (ls2k0500/ls2k1000/ls2k2000)
have a similar clock structure, and I support them to be configured with
different parameters (e.g., register offsets, etc.).
To make it easier to add support for different SoCs, I refactored the
original driver to make the whole driver as understandable as possible.
Briefly, I have divided all clocks into three categories according to
their properties and their parent clocks: Independent PLLs, clocks based
on frequency scales, and clock dividers.
Thanks.
Binbin Zhou (8):
dt-bindings: clock: add Loongson-2K expand clock index
clk: clk-loongson2: Refactor driver for adding new platforms
dt-bindings: clock: loongson2: add Loongson-2K0500 compatible
clk: clk-loongson2: Add Loongson-2K0500 clock support
dt-bindings: clock: loongson2: add Loongson-2K2000 compatible
clk: clk-loongson2: Add Loongson-2K2000 clock support
LoongArch: dts: Add clock support to Loongson-2K0500
LoongArch: dts: Add clock support to Loongson-2K2000
.../bindings/clock/loongson,ls2k-clk.yaml | 4 +-
.../boot/dts/loongson-2k0500-ref.dts | 4 +
arch/loongarch/boot/dts/loongson-2k0500.dtsi | 57 +-
.../boot/dts/loongson-2k2000-ref.dts | 4 +
arch/loongarch/boot/dts/loongson-2k2000.dtsi | 19 +-
drivers/clk/clk-loongson2.c | 549 ++++++++++--------
include/dt-bindings/clock/loongson,ls2k-clk.h | 58 +-
7 files changed, 410 insertions(+), 285 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v1 1/8] dt-bindings: clock: add Loongson-2K expand clock index
2024-03-26 9:00 [PATCH v1 0/8] Add Loongson-2k0500 and Loongson-2k2000 clock support Binbin Zhou
@ 2024-03-26 9:01 ` Binbin Zhou
2024-03-26 18:54 ` Conor Dooley
2024-03-26 9:01 ` [PATCH v1 2/8] clk: clk-loongson2: Refactor driver for adding new platforms Binbin Zhou
` (6 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Binbin Zhou @ 2024-03-26 9:01 UTC (permalink / raw
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou
The Loongson-2K2000 has more clock indexs, such as clock gates.
This patch adds these clock indexes.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
include/dt-bindings/clock/loongson,ls2k-clk.h | 58 +++++++++++++------
1 file changed, 39 insertions(+), 19 deletions(-)
diff --git a/include/dt-bindings/clock/loongson,ls2k-clk.h b/include/dt-bindings/clock/loongson,ls2k-clk.h
index 3bc4dfc193c2..59546c7a1c5e 100644
--- a/include/dt-bindings/clock/loongson,ls2k-clk.h
+++ b/include/dt-bindings/clock/loongson,ls2k-clk.h
@@ -7,24 +7,44 @@
#ifndef __DT_BINDINGS_CLOCK_LOONGSON2_H
#define __DT_BINDINGS_CLOCK_LOONGSON2_H
-#define LOONGSON2_REF_100M 0
-#define LOONGSON2_NODE_PLL 1
-#define LOONGSON2_DDR_PLL 2
-#define LOONGSON2_DC_PLL 3
-#define LOONGSON2_PIX0_PLL 4
-#define LOONGSON2_PIX1_PLL 5
-#define LOONGSON2_NODE_CLK 6
-#define LOONGSON2_HDA_CLK 7
-#define LOONGSON2_GPU_CLK 8
-#define LOONGSON2_DDR_CLK 9
-#define LOONGSON2_GMAC_CLK 10
-#define LOONGSON2_DC_CLK 11
-#define LOONGSON2_APB_CLK 12
-#define LOONGSON2_USB_CLK 13
-#define LOONGSON2_SATA_CLK 14
-#define LOONGSON2_PIX0_CLK 15
-#define LOONGSON2_PIX1_CLK 16
-#define LOONGSON2_BOOT_CLK 17
-#define LOONGSON2_CLK_END 18
+#define LOONGSON2_REF_100M 0
+#define LOONGSON2_NODE_PLL 1
+#define LOONGSON2_DDR_PLL 2
+#define LOONGSON2_DC_PLL 3
+#define LOONGSON2_PIX0_PLL 4
+#define LOONGSON2_PIX1_PLL 5
+#define LOONGSON2_NODE_CLK 6
+#define LOONGSON2_HDA_CLK 7
+#define LOONGSON2_GPU_CLK 8
+#define LOONGSON2_DDR_CLK 9
+#define LOONGSON2_GMAC_CLK 10
+#define LOONGSON2_DC_CLK 11
+#define LOONGSON2_APB_CLK 12
+#define LOONGSON2_USB_CLK 13
+#define LOONGSON2_SATA_CLK 14
+#define LOONGSON2_PIX0_CLK 15
+#define LOONGSON2_PIX1_CLK 16
+#define LOONGSON2_BOOT_CLK 17
+
+/* Loongson-2K2000 */
+#define LOONGSON2_OUT0_GATE 18
+#define LOONGSON2_GMAC_GATE 19
+#define LOONGSON2_RIO_GATE 20
+#define LOONGSON2_DC_GATE 21
+#define LOONGSON2_GPU_GATE 22
+#define LOONGSON2_DDR_GATE 23
+#define LOONGSON2_HDA_GATE 24
+#define LOONGSON2_NODE_GATE 25
+#define LOONGSON2_EMMC_GATE 26
+#define LOONGSON2_PIX0_GATE 27
+#define LOONGSON2_PIX1_GATE 28
+#define LOONGSON2_OUT0_CLK 29
+#define LOONGSON2_RIO_CLK 30
+#define LOONGSON2_EMMC_CLK 31
+#define LOONGSON2_DES_CLK 32
+#define LOONGSON2_I2S_CLK 33
+#define LOONGSON2_MISC_CLK 34
+
+#define LOONGSON2_CLK_END 35
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v1 2/8] clk: clk-loongson2: Refactor driver for adding new platforms
2024-03-26 9:00 [PATCH v1 0/8] Add Loongson-2k0500 and Loongson-2k2000 clock support Binbin Zhou
2024-03-26 9:01 ` [PATCH v1 1/8] dt-bindings: clock: add Loongson-2K expand clock index Binbin Zhou
@ 2024-03-26 9:01 ` Binbin Zhou
2024-03-26 9:01 ` [PATCH v1 3/8] dt-bindings: clock: loongson2: add Loongson-2K0500 compatible Binbin Zhou
` (5 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Binbin Zhou @ 2024-03-26 9:01 UTC (permalink / raw
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou
The driver only supported loongson-2K1000 at first, but the clock
structure of loongson-2K0500 and loongson-2K2000 are actually similar,
and I tried to refactor the whole driver to adjust to the addition of
the new platform.
Briefly, I have divided all clocks into three categories according to
their properties and their parent clocks: Independent PLLs, clocks based
on frequency scales, and clock dividers.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
drivers/clk/clk-loongson2.c | 459 ++++++++++++++++--------------------
1 file changed, 199 insertions(+), 260 deletions(-)
diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
index bacdcbb287ac..00e384290314 100644
--- a/drivers/clk/clk-loongson2.c
+++ b/drivers/clk/clk-loongson2.c
@@ -6,6 +6,7 @@
#include <linux/err.h>
#include <linux/init.h>
+#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/module.h>
@@ -13,317 +14,254 @@
#include <linux/io-64-nonatomic-lo-hi.h>
#include <dt-bindings/clock/loongson,ls2k-clk.h>
-#define LOONGSON2_PLL_MULT_SHIFT 32
-#define LOONGSON2_PLL_MULT_WIDTH 10
-#define LOONGSON2_PLL_DIV_SHIFT 26
-#define LOONGSON2_PLL_DIV_WIDTH 6
-#define LOONGSON2_APB_FREQSCALE_SHIFT 20
-#define LOONGSON2_APB_FREQSCALE_WIDTH 3
-#define LOONGSON2_USB_FREQSCALE_SHIFT 16
-#define LOONGSON2_USB_FREQSCALE_WIDTH 3
-#define LOONGSON2_SATA_FREQSCALE_SHIFT 12
-#define LOONGSON2_SATA_FREQSCALE_WIDTH 3
-#define LOONGSON2_BOOT_FREQSCALE_SHIFT 8
-#define LOONGSON2_BOOT_FREQSCALE_WIDTH 3
-
-static void __iomem *loongson2_pll_base;
-
static const struct clk_parent_data pdata[] = {
- { .fw_name = "ref_100m",},
+ { .fw_name = "ref_100m", },
};
-static struct clk_hw *loongson2_clk_register(struct device *dev,
- const char *name,
- const char *parent_name,
- const struct clk_ops *ops,
- unsigned long flags)
-{
- int ret;
- struct clk_hw *hw;
- struct clk_init_data init = { };
-
- hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
- if (!hw)
- return ERR_PTR(-ENOMEM);
-
- init.name = name;
- init.ops = ops;
- init.flags = flags;
- init.num_parents = 1;
-
- if (!parent_name)
- init.parent_data = pdata;
- else
- init.parent_names = &parent_name;
-
- hw->init = &init;
-
- ret = devm_clk_hw_register(dev, hw);
- if (ret)
- hw = ERR_PTR(ret);
-
- return hw;
-}
-
-static unsigned long loongson2_calc_pll_rate(int offset, unsigned long rate)
-{
- u64 val;
- u32 mult, div;
-
- val = readq(loongson2_pll_base + offset);
-
- mult = (val >> LOONGSON2_PLL_MULT_SHIFT) &
- clk_div_mask(LOONGSON2_PLL_MULT_WIDTH);
- div = (val >> LOONGSON2_PLL_DIV_SHIFT) &
- clk_div_mask(LOONGSON2_PLL_DIV_WIDTH);
-
- return div_u64((u64)rate * mult, div);
-}
-
-static unsigned long loongson2_node_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return loongson2_calc_pll_rate(0x0, parent_rate);
-}
-
-static const struct clk_ops loongson2_node_clk_ops = {
- .recalc_rate = loongson2_node_recalc_rate,
+enum loongson2_clk_type {
+ CLK_TYPE_PLL,
+ CLK_TYPE_SCALE,
+ CLK_TYPE_DIVIDER,
+ CLK_TYPE_NONE,
};
-static unsigned long loongson2_ddr_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return loongson2_calc_pll_rate(0x10, parent_rate);
-}
+struct loongson2_clk_provider {
+ void __iomem *base;
+ struct device *dev;
+ struct clk_hw_onecell_data clk_data;
+ spinlock_t clk_lock; /* protect access to DIV registers */
+};
-static const struct clk_ops loongson2_ddr_clk_ops = {
- .recalc_rate = loongson2_ddr_recalc_rate,
+struct loongson2_clk_data {
+ struct clk_hw hw;
+ void __iomem *reg;
+ u8 div_shift;
+ u8 div_width;
+ u8 mult_shift;
+ u8 mult_width;
};
-static unsigned long loongson2_dc_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return loongson2_calc_pll_rate(0x20, parent_rate);
-}
+struct loongson2_clk_board_info {
+ u8 id;
+ enum loongson2_clk_type type;
+ const char *name;
+ const char *parent_name;
+ u8 reg_offset;
+ u8 div_shift;
+ u8 div_width;
+ u8 mult_shift;
+ u8 mult_width;
+};
-static const struct clk_ops loongson2_dc_clk_ops = {
- .recalc_rate = loongson2_dc_recalc_rate,
+#define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \
+ { \
+ .id = _id, \
+ .type = CLK_TYPE_DIVIDER, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .reg_offset = _offset, \
+ .div_shift = _dshift, \
+ .div_width = _dwidth, \
+ }
+
+#define CLK_PLL(_id, _name, _offset, _mshift, _mwidth, \
+ _dshift, _dwidth) \
+ { \
+ .id = _id, \
+ .type = CLK_TYPE_PLL, \
+ .name = _name, \
+ .parent_name = NULL, \
+ .reg_offset = _offset, \
+ .mult_shift = _mshift, \
+ .mult_width = _mwidth, \
+ .div_shift = _dshift, \
+ .div_width = _dwidth, \
+ }
+
+#define CLK_SCALE(_id, _name, _pname, _offset, \
+ _dshift, _dwidth) \
+ { \
+ .id = _id, \
+ .type = CLK_TYPE_SCALE, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .reg_offset = _offset, \
+ .div_shift = _dshift, \
+ .div_width = _dwidth, \
+ }
+
+static const struct loongson2_clk_board_info ls2k1000_clks[] = {
+ CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 32, 10, 26, 6),
+ CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x10, 32, 10, 26, 6),
+ CLK_PLL(LOONGSON2_DC_PLL, "pll_dc", 0x20, 32, 10, 26, 6),
+ CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x30, 32, 10, 26, 6),
+ CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x40, 32, 10, 26, 6),
+ CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "pll_node", 0x8, 0, 6),
+ CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "pll_ddr", 0x18, 0, 6),
+ CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "pll_ddr", 0x18, 22, 6),
+ /*
+ * The hda clk divisor in the upper 32bits and the clk-prodiver
+ * layer code doesn't support 64bit io operation thus a conversion
+ * is required that subtract shift by 32 and add 4byte to the hda
+ * address
+ */
+ CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "pll_ddr", 0x22, 12, 7),
+ CLK_DIV(LOONGSON2_DC_CLK, "clk_dc", "pll_dc", 0x28, 0, 6),
+ CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "pll_dc", 0x28, 22, 6),
+ CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x38, 0, 6),
+ CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x38, 0, 6),
+ CLK_SCALE(LOONGSON2_BOOT_CLK, "clk_boot", NULL, 0x50, 8, 3),
+ CLK_SCALE(LOONGSON2_SATA_CLK, "clk_sata", "clk_gmac", 0x50, 12, 3),
+ CLK_SCALE(LOONGSON2_USB_CLK, "clk_usb", "clk_gmac", 0x50, 16, 3),
+ CLK_SCALE(LOONGSON2_APB_CLK, "clk_apb", "clk_gmac", 0x50, 20, 3),
+ { /* Sentinel */ },
};
-static unsigned long loongson2_pix0_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
+static inline struct loongson2_clk_data *to_loongson2_clk(struct clk_hw *hw)
{
- return loongson2_calc_pll_rate(0x30, parent_rate);
+ return container_of(hw, struct loongson2_clk_data, hw);
}
-static const struct clk_ops loongson2_pix0_clk_ops = {
- .recalc_rate = loongson2_pix0_recalc_rate,
-};
-
-static unsigned long loongson2_pix1_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
+static inline unsigned long loongson2_rate_part(u64 val, u8 shift, u8 width)
{
- return loongson2_calc_pll_rate(0x40, parent_rate);
+ return (val & GENMASK(shift + width - 1, shift)) >> shift;
}
-static const struct clk_ops loongson2_pix1_clk_ops = {
- .recalc_rate = loongson2_pix1_recalc_rate,
-};
-
-static unsigned long loongson2_calc_rate(unsigned long rate,
- int shift, int width)
+static unsigned long loongson2_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
{
- u64 val;
- u32 mult;
-
- val = readq(loongson2_pll_base + 0x50);
+ u64 val, mult, div;
+ struct loongson2_clk_data *clk = to_loongson2_clk(hw);
- mult = (val >> shift) & clk_div_mask(width);
+ val = readq(clk->reg);
+ mult = loongson2_rate_part(val, clk->mult_shift, clk->mult_width);
+ div = loongson2_rate_part(val, clk->div_shift, clk->div_width);
- return div_u64((u64)rate * (mult + 1), 8);
-}
-
-static unsigned long loongson2_boot_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return loongson2_calc_rate(parent_rate,
- LOONGSON2_BOOT_FREQSCALE_SHIFT,
- LOONGSON2_BOOT_FREQSCALE_WIDTH);
+ return div_u64((u64)parent_rate * mult, div);
}
-static const struct clk_ops loongson2_boot_clk_ops = {
- .recalc_rate = loongson2_boot_recalc_rate,
+static const struct clk_ops loongson2_pll_recalc_ops = {
+ .recalc_rate = loongson2_pll_recalc_rate,
};
-static unsigned long loongson2_apb_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
+static unsigned long loongson2_freqscale_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
{
- return loongson2_calc_rate(parent_rate,
- LOONGSON2_APB_FREQSCALE_SHIFT,
- LOONGSON2_APB_FREQSCALE_WIDTH);
-}
+ u64 val, mult;
+ struct loongson2_clk_data *clk = to_loongson2_clk(hw);
-static const struct clk_ops loongson2_apb_clk_ops = {
- .recalc_rate = loongson2_apb_recalc_rate,
-};
+ val = readq(clk->reg);
+ mult = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;
-static unsigned long loongson2_usb_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return loongson2_calc_rate(parent_rate,
- LOONGSON2_USB_FREQSCALE_SHIFT,
- LOONGSON2_USB_FREQSCALE_WIDTH);
+ return div_u64((u64)parent_rate * mult, 8);
}
-static const struct clk_ops loongson2_usb_clk_ops = {
- .recalc_rate = loongson2_usb_recalc_rate,
+static const struct clk_ops loongson2_freqscale_recalc_ops = {
+ .recalc_rate = loongson2_freqscale_recalc_rate,
};
-static unsigned long loongson2_sata_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
+static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider *clp,
+ const struct loongson2_clk_board_info *cld,
+ const struct clk_ops *ops)
{
- return loongson2_calc_rate(parent_rate,
- LOONGSON2_SATA_FREQSCALE_SHIFT,
- LOONGSON2_SATA_FREQSCALE_WIDTH);
-}
+ int ret;
+ struct clk_hw *hw;
+ struct loongson2_clk_data *clk;
+ struct clk_init_data init = { };
-static const struct clk_ops loongson2_sata_clk_ops = {
- .recalc_rate = loongson2_sata_recalc_rate,
-};
+ clk = devm_kzalloc(clp->dev, sizeof(*clk), GFP_KERNEL);
+ if (!clk)
+ return ERR_PTR(-ENOMEM);
-static inline int loongson2_check_clk_hws(struct clk_hw *clks[], unsigned int count)
-{
- unsigned int i;
+ init.name = cld->name;
+ init.ops = ops;
+ init.flags = 0;
+ init.num_parents = 1;
- for (i = 0; i < count; i++)
- if (IS_ERR(clks[i])) {
- pr_err("Loongson2 clk %u: register failed with %ld\n",
- i, PTR_ERR(clks[i]));
- return PTR_ERR(clks[i]);
- }
+ if (!cld->parent_name)
+ init.parent_data = pdata;
+ else
+ init.parent_names = &cld->parent_name;
+
+ clk->reg = clp->base + cld->reg_offset;
+ clk->div_shift = cld->div_shift;
+ clk->div_width = cld->div_width;
+ clk->mult_shift = cld->mult_shift;
+ clk->mult_width = cld->mult_width;
+ clk->hw.init = &init;
- return 0;
+ hw = &clk->hw;
+ ret = devm_clk_hw_register(clp->dev, hw);
+ if (ret)
+ clk = ERR_PTR(ret);
+
+ return hw;
}
static int loongson2_clk_probe(struct platform_device *pdev)
{
- int ret;
- struct clk_hw **hws;
- struct clk_hw_onecell_data *clk_hw_data;
- spinlock_t loongson2_clk_lock;
+ int i, clks_num = 0;
+ struct clk_hw *hw;
struct device *dev = &pdev->dev;
+ struct loongson2_clk_provider *clp;
+ const struct loongson2_clk_board_info *p, *data;
- loongson2_pll_base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(loongson2_pll_base))
- return PTR_ERR(loongson2_pll_base);
-
- clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, LOONGSON2_CLK_END),
- GFP_KERNEL);
- if (WARN_ON(!clk_hw_data))
- return -ENOMEM;
-
- clk_hw_data->num = LOONGSON2_CLK_END;
- hws = clk_hw_data->hws;
-
- hws[LOONGSON2_NODE_PLL] = loongson2_clk_register(dev, "node_pll",
- NULL,
- &loongson2_node_clk_ops, 0);
-
- hws[LOONGSON2_DDR_PLL] = loongson2_clk_register(dev, "ddr_pll",
- NULL,
- &loongson2_ddr_clk_ops, 0);
+ data = device_get_match_data(dev);
+ if (!data)
+ return -EINVAL;
- hws[LOONGSON2_DC_PLL] = loongson2_clk_register(dev, "dc_pll",
- NULL,
- &loongson2_dc_clk_ops, 0);
+ for (p = data; p->name; p++)
+ clks_num++;
- hws[LOONGSON2_PIX0_PLL] = loongson2_clk_register(dev, "pix0_pll",
- NULL,
- &loongson2_pix0_clk_ops, 0);
-
- hws[LOONGSON2_PIX1_PLL] = loongson2_clk_register(dev, "pix1_pll",
- NULL,
- &loongson2_pix1_clk_ops, 0);
+ clp = devm_kzalloc(dev, struct_size(clp, clk_data.hws, clks_num),
+ GFP_KERNEL);
+ if (!clp)
+ return -ENOMEM;
- hws[LOONGSON2_BOOT_CLK] = loongson2_clk_register(dev, "boot",
- NULL,
- &loongson2_boot_clk_ops, 0);
+ clp->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(clp->base))
+ return PTR_ERR(clp->base);
+
+ spin_lock_init(&clp->clk_lock);
+ clp->clk_data.num = clks_num + 1;
+ clp->dev = dev;
+
+ for (i = 0; i < clks_num; i++) {
+ p = &data[i];
+ switch (p->type) {
+ case CLK_TYPE_PLL:
+ hw = loongson2_clk_register(clp, p,
+ &loongson2_pll_recalc_ops);
+ break;
+ case CLK_TYPE_SCALE:
+ hw = loongson2_clk_register(clp, p,
+ &loongson2_freqscale_recalc_ops);
+ break;
+ case CLK_TYPE_DIVIDER:
+ hw = devm_clk_hw_register_divider(dev, p->name,
+ p->parent_name, 0,
+ clp->base + p->reg_offset,
+ p->div_shift, p->div_width,
+ CLK_DIVIDER_ONE_BASED,
+ &clp->clk_lock);
+ break;
+ default:
+ return dev_err_probe(dev, -EINVAL, "Invalid clk type\n");
+ }
- hws[LOONGSON2_NODE_CLK] = devm_clk_hw_register_divider(dev, "node",
- "node_pll", 0,
- loongson2_pll_base + 0x8, 0,
- 6, CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
+ if (IS_ERR(hw))
+ return dev_err_probe(dev, PTR_ERR(hw),
+ "Register clk: %s, type: %u failed!\n",
+ p->name, p->type);
- /*
- * The hda clk divisor in the upper 32bits and the clk-prodiver
- * layer code doesn't support 64bit io operation thus a conversion
- * is required that subtract shift by 32 and add 4byte to the hda
- * address
- */
- hws[LOONGSON2_HDA_CLK] = devm_clk_hw_register_divider(dev, "hda",
- "ddr_pll", 0,
- loongson2_pll_base + 0x22, 12,
- 7, CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
-
- hws[LOONGSON2_GPU_CLK] = devm_clk_hw_register_divider(dev, "gpu",
- "ddr_pll", 0,
- loongson2_pll_base + 0x18, 22,
- 6, CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
-
- hws[LOONGSON2_DDR_CLK] = devm_clk_hw_register_divider(dev, "ddr",
- "ddr_pll", 0,
- loongson2_pll_base + 0x18, 0,
- 6, CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
-
- hws[LOONGSON2_GMAC_CLK] = devm_clk_hw_register_divider(dev, "gmac",
- "dc_pll", 0,
- loongson2_pll_base + 0x28, 22,
- 6, CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
-
- hws[LOONGSON2_DC_CLK] = devm_clk_hw_register_divider(dev, "dc",
- "dc_pll", 0,
- loongson2_pll_base + 0x28, 0,
- 6, CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
-
- hws[LOONGSON2_APB_CLK] = loongson2_clk_register(dev, "apb",
- "gmac",
- &loongson2_apb_clk_ops, 0);
-
- hws[LOONGSON2_USB_CLK] = loongson2_clk_register(dev, "usb",
- "gmac",
- &loongson2_usb_clk_ops, 0);
-
- hws[LOONGSON2_SATA_CLK] = loongson2_clk_register(dev, "sata",
- "gmac",
- &loongson2_sata_clk_ops, 0);
-
- hws[LOONGSON2_PIX0_CLK] = clk_hw_register_divider(NULL, "pix0",
- "pix0_pll", 0,
- loongson2_pll_base + 0x38, 0, 6,
- CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
-
- hws[LOONGSON2_PIX1_CLK] = clk_hw_register_divider(NULL, "pix1",
- "pix1_pll", 0,
- loongson2_pll_base + 0x48, 0, 6,
- CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
-
- ret = loongson2_check_clk_hws(hws, LOONGSON2_CLK_END);
- if (ret)
- return ret;
+ clp->clk_data.hws[p->id] = hw;
+ }
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data);
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clp->clk_data);
}
static const struct of_device_id loongson2_clk_match_table[] = {
- { .compatible = "loongson,ls2k-clk" },
+ { .compatible = "loongson,ls2k-clk", .data = &ls2k1000_clks },
{ }
};
MODULE_DEVICE_TABLE(of, loongson2_clk_match_table);
@@ -338,4 +276,5 @@ static struct platform_driver loongson2_clk_driver = {
module_platform_driver(loongson2_clk_driver);
MODULE_DESCRIPTION("Loongson2 clock driver");
+MODULE_AUTHOR("Loongson Technology Corporation Limited");
MODULE_LICENSE("GPL");
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v1 3/8] dt-bindings: clock: loongson2: add Loongson-2K0500 compatible
2024-03-26 9:00 [PATCH v1 0/8] Add Loongson-2k0500 and Loongson-2k2000 clock support Binbin Zhou
2024-03-26 9:01 ` [PATCH v1 1/8] dt-bindings: clock: add Loongson-2K expand clock index Binbin Zhou
2024-03-26 9:01 ` [PATCH v1 2/8] clk: clk-loongson2: Refactor driver for adding new platforms Binbin Zhou
@ 2024-03-26 9:01 ` Binbin Zhou
2024-03-26 18:56 ` Conor Dooley
2024-03-26 9:01 ` [PATCH v1 4/8] clk: clk-loongson2: Add Loongson-2K0500 clock support Binbin Zhou
` (4 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Binbin Zhou @ 2024-03-26 9:01 UTC (permalink / raw
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou
Add the devicetree compatible for Loongson-2K0500 clocks.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
index 63a59015987e..83baee40e200 100644
--- a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
@@ -16,7 +16,8 @@ description: |
properties:
compatible:
enum:
- - loongson,ls2k-clk
+ - loongson,ls2k0500-clk
+ - loongson,ls2k-clk # This is for Loongson-2K1000
reg:
maxItems: 1
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v1 4/8] clk: clk-loongson2: Add Loongson-2K0500 clock support
2024-03-26 9:00 [PATCH v1 0/8] Add Loongson-2k0500 and Loongson-2k2000 clock support Binbin Zhou
` (2 preceding siblings ...)
2024-03-26 9:01 ` [PATCH v1 3/8] dt-bindings: clock: loongson2: add Loongson-2K0500 compatible Binbin Zhou
@ 2024-03-26 9:01 ` Binbin Zhou
2024-03-26 9:01 ` [PATCH v1 5/8] dt-bindings: clock: loongson2: add Loongson-2K2000 compatible Binbin Zhou
` (3 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Binbin Zhou @ 2024-03-26 9:01 UTC (permalink / raw
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou
The Loongson-2K0500 and Loongson-2K1000 clock is similar, we add its
support by different configurations.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
drivers/clk/clk-loongson2.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
index 00e384290314..4e3b287ff9a0 100644
--- a/drivers/clk/clk-loongson2.c
+++ b/drivers/clk/clk-loongson2.c
@@ -90,6 +90,27 @@ struct loongson2_clk_board_info {
.div_width = _dwidth, \
}
+static const struct loongson2_clk_board_info ls2k0500_clks[] = {
+ CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 16, 8, 8, 6),
+ CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x8, 16, 8, 8, 6),
+ CLK_PLL(LOONGSON2_DC_PLL, "pll_soc", 0x10, 16, 8, 8, 6),
+ CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x18, 16, 8, 8, 6),
+ CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x20, 16, 8, 8, 6),
+ CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "pll_node", 0, 24, 6),
+ CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "pll_ddr", 0x8, 24, 6),
+ CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "pll_ddr", 0xc, 8, 6),
+ CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "pll_soc", 0x10, 24, 6),
+ CLK_DIV(LOONGSON2_DC_CLK, "clk_sb", "pll_soc", 0x14, 0, 6),
+ CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "pll_soc", 0x14, 8, 6),
+ CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x18, 24, 6),
+ CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x20, 24, 6),
+ CLK_SCALE(LOONGSON2_BOOT_CLK, "clk_boot", "clk_sb", 0x28, 8, 3),
+ CLK_SCALE(LOONGSON2_SATA_CLK, "clk_sata", "clk_sb", 0x28, 12, 3),
+ CLK_SCALE(LOONGSON2_USB_CLK, "clk_usb", "clk_sb", 0x28, 16, 3),
+ CLK_SCALE(LOONGSON2_APB_CLK, "clk_apb", "clk_sb", 0x28, 20, 3),
+ { /* Sentinel */ },
+};
+
static const struct loongson2_clk_board_info ls2k1000_clks[] = {
CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 32, 10, 26, 6),
CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x10, 32, 10, 26, 6),
@@ -261,6 +282,7 @@ static int loongson2_clk_probe(struct platform_device *pdev)
}
static const struct of_device_id loongson2_clk_match_table[] = {
+ { .compatible = "loongson,ls2k0500-clk", .data = &ls2k0500_clks },
{ .compatible = "loongson,ls2k-clk", .data = &ls2k1000_clks },
{ }
};
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v1 5/8] dt-bindings: clock: loongson2: add Loongson-2K2000 compatible
2024-03-26 9:00 [PATCH v1 0/8] Add Loongson-2k0500 and Loongson-2k2000 clock support Binbin Zhou
` (3 preceding siblings ...)
2024-03-26 9:01 ` [PATCH v1 4/8] clk: clk-loongson2: Add Loongson-2K0500 clock support Binbin Zhou
@ 2024-03-26 9:01 ` Binbin Zhou
2024-03-26 18:56 ` Conor Dooley
2024-03-26 9:01 ` [PATCH v1 6/8] clk: clk-loongson2: Add Loongson-2K2000 clock support Binbin Zhou
` (2 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Binbin Zhou @ 2024-03-26 9:01 UTC (permalink / raw
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou
Add the devicetree compatible for Loongson-2K2000 clocks.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
index 83baee40e200..4f79cdb417ab 100644
--- a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
@@ -18,6 +18,7 @@ properties:
enum:
- loongson,ls2k0500-clk
- loongson,ls2k-clk # This is for Loongson-2K1000
+ - loongson,ls2k2000-clk
reg:
maxItems: 1
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v1 6/8] clk: clk-loongson2: Add Loongson-2K2000 clock support
2024-03-26 9:00 [PATCH v1 0/8] Add Loongson-2k0500 and Loongson-2k2000 clock support Binbin Zhou
` (4 preceding siblings ...)
2024-03-26 9:01 ` [PATCH v1 5/8] dt-bindings: clock: loongson2: add Loongson-2K2000 compatible Binbin Zhou
@ 2024-03-26 9:01 ` Binbin Zhou
2024-03-26 9:01 ` [PATCH v1 7/8] LoongArch: dts: Add clock support to Loongson-2K0500 Binbin Zhou
2024-03-26 9:01 ` [PATCH v1 8/8] LoongArch: dts: Add clock support to Loongson-2K2000 Binbin Zhou
7 siblings, 0 replies; 14+ messages in thread
From: Binbin Zhou @ 2024-03-26 9:01 UTC (permalink / raw
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou
The Loongson-2K2000 and Loongson-2K1000 clock is similar, we add its
support by different configurations.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
drivers/clk/clk-loongson2.c | 72 +++++++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
index 4e3b287ff9a0..271de0e10518 100644
--- a/drivers/clk/clk-loongson2.c
+++ b/drivers/clk/clk-loongson2.c
@@ -22,6 +22,8 @@ enum loongson2_clk_type {
CLK_TYPE_PLL,
CLK_TYPE_SCALE,
CLK_TYPE_DIVIDER,
+ CLK_TYPE_GATE,
+ CLK_TYPE_FIXED,
CLK_TYPE_NONE,
};
@@ -46,11 +48,13 @@ struct loongson2_clk_board_info {
enum loongson2_clk_type type;
const char *name;
const char *parent_name;
+ unsigned long fixed_rate;
u8 reg_offset;
u8 div_shift;
u8 div_width;
u8 mult_shift;
u8 mult_width;
+ u8 bit_idx;
};
#define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \
@@ -90,6 +94,25 @@ struct loongson2_clk_board_info {
.div_width = _dwidth, \
}
+#define CLK_GATE(_id, _name, _pname, _offset, _bidx) \
+ { \
+ .id = _id, \
+ .type = CLK_TYPE_GATE, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .reg_offset = _offset, \
+ .bit_idx = _bidx, \
+ }
+
+#define CLK_FIXED(_id, _name, _pname, _rate) \
+ { \
+ .id = _id, \
+ .type = CLK_TYPE_FIXED, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .fixed_rate = _rate, \
+ }
+
static const struct loongson2_clk_board_info ls2k0500_clks[] = {
CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 16, 8, 8, 6),
CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x8, 16, 8, 8, 6),
@@ -138,6 +161,44 @@ static const struct loongson2_clk_board_info ls2k1000_clks[] = {
{ /* Sentinel */ },
};
+static const struct loongson2_clk_board_info ls2k2000_clks[] = {
+ CLK_PLL(LOONGSON2_DC_PLL, "pll_0", 0, 21, 9, 32, 6),
+ CLK_PLL(LOONGSON2_DDR_PLL, "pll_1", 0x10, 21, 9, 32, 6),
+ CLK_PLL(LOONGSON2_NODE_PLL, "pll_2", 0x20, 21, 9, 32, 6),
+ CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x30, 21, 9, 32, 6),
+ CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x40, 21, 9, 32, 6),
+ CLK_GATE(LOONGSON2_OUT0_GATE, "out0_gate", "pll_0", 0, 40),
+ CLK_GATE(LOONGSON2_GMAC_GATE, "gmac_gate", "pll_0", 0, 41),
+ CLK_GATE(LOONGSON2_RIO_GATE, "rio_gate", "pll_0", 0, 42),
+ CLK_GATE(LOONGSON2_DC_GATE, "dc_gate", "pll_1", 0x10, 40),
+ CLK_GATE(LOONGSON2_DDR_GATE, "ddr_gate", "pll_1", 0x10, 41),
+ CLK_GATE(LOONGSON2_GPU_GATE, "gpu_gate", "pll_1", 0x10, 42),
+ CLK_GATE(LOONGSON2_HDA_GATE, "hda_gate", "pll_2", 0x20, 40),
+ CLK_GATE(LOONGSON2_NODE_GATE, "node_gate", "pll_2", 0x20, 41),
+ CLK_GATE(LOONGSON2_EMMC_GATE, "emmc_gate", "pll_2", 0x20, 42),
+ CLK_GATE(LOONGSON2_PIX0_GATE, "pix0_gate", "pll_pix0", 0x30, 40),
+ CLK_GATE(LOONGSON2_PIX1_GATE, "pix1_gate", "pll_pix1", 0x40, 40),
+ CLK_DIV(LOONGSON2_OUT0_CLK, "clk_out0", "out0_gate", 0, 0, 6),
+ CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "gmac_gate", 0, 7, 6),
+ CLK_DIV(LOONGSON2_RIO_CLK, "clk_rio", "rio_gate", 0, 14, 6),
+ CLK_DIV(LOONGSON2_DC_CLK, "clk_dc", "dc_gate", 0x10, 0, 6),
+ CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "gpu_gate", 0x10, 7, 6),
+ CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "ddr_gate", 0x10, 14, 6),
+ CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "hda_gate", 0x20, 0, 6),
+ CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "node_gate", 0x20, 7, 6),
+ CLK_DIV(LOONGSON2_EMMC_CLK, "clk_emmc", "emmc_gate", 0x20, 14, 6),
+ CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x30, 0, 6),
+ CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x40, 0, 6),
+ CLK_SCALE(LOONGSON2_SATA_CLK, "clk_sata", "clk_out0", 0x50, 12, 3),
+ CLK_SCALE(LOONGSON2_USB_CLK, "clk_usb", "clk_out0", 0x50, 16, 3),
+ CLK_SCALE(LOONGSON2_APB_CLK, "clk_apb", "clk_node", 0x50, 20, 3),
+ CLK_SCALE(LOONGSON2_BOOT_CLK, "clk_boot", NULL, 0x50, 23, 3),
+ CLK_SCALE(LOONGSON2_DES_CLK, "clk_des", "clk_node", 0x50, 40, 3),
+ CLK_SCALE(LOONGSON2_I2S_CLK, "clk_i2s", "clk_node", 0x50, 44, 3),
+ CLK_FIXED(LOONGSON2_MISC_CLK, "clk_misc", NULL, 50000000),
+ { /* Sentinel */ },
+};
+
static inline struct loongson2_clk_data *to_loongson2_clk(struct clk_hw *hw)
{
return container_of(hw, struct loongson2_clk_data, hw);
@@ -266,6 +327,16 @@ static int loongson2_clk_probe(struct platform_device *pdev)
CLK_DIVIDER_ONE_BASED,
&clp->clk_lock);
break;
+ case CLK_TYPE_GATE:
+ hw = devm_clk_hw_register_gate(dev, p->name, p->parent_name, 0,
+ clp->base + p->reg_offset,
+ p->bit_idx, 0,
+ &clp->clk_lock);
+ break;
+ case CLK_TYPE_FIXED:
+ hw = clk_hw_register_fixed_rate_parent_data(dev, p->name, pdata,
+ 0, p->fixed_rate);
+ break;
default:
return dev_err_probe(dev, -EINVAL, "Invalid clk type\n");
}
@@ -284,6 +355,7 @@ static int loongson2_clk_probe(struct platform_device *pdev)
static const struct of_device_id loongson2_clk_match_table[] = {
{ .compatible = "loongson,ls2k0500-clk", .data = &ls2k0500_clks },
{ .compatible = "loongson,ls2k-clk", .data = &ls2k1000_clks },
+ { .compatible = "loongson,ls2k2000-clk", .data = &ls2k2000_clks },
{ }
};
MODULE_DEVICE_TABLE(of, loongson2_clk_match_table);
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v1 7/8] LoongArch: dts: Add clock support to Loongson-2K0500
2024-03-26 9:00 [PATCH v1 0/8] Add Loongson-2k0500 and Loongson-2k2000 clock support Binbin Zhou
` (5 preceding siblings ...)
2024-03-26 9:01 ` [PATCH v1 6/8] clk: clk-loongson2: Add Loongson-2K2000 clock support Binbin Zhou
@ 2024-03-26 9:01 ` Binbin Zhou
2024-03-26 9:01 ` [PATCH v1 8/8] LoongArch: dts: Add clock support to Loongson-2K2000 Binbin Zhou
7 siblings, 0 replies; 14+ messages in thread
From: Binbin Zhou @ 2024-03-26 9:01 UTC (permalink / raw
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou
The module is supported, enable it.
Also, add the dma node associated with it.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
.../boot/dts/loongson-2k0500-ref.dts | 4 ++
arch/loongarch/boot/dts/loongson-2k0500.dtsi | 57 ++++++++++++++++++-
2 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/arch/loongarch/boot/dts/loongson-2k0500-ref.dts b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
index 8aefb0c12672..62dad6297e82 100644
--- a/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
+++ b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
@@ -41,6 +41,10 @@ linux,cma {
};
};
+&clk {
+ status = "okay";
+};
+
&gmac0 {
status = "okay";
diff --git a/arch/loongarch/boot/dts/loongson-2k0500.dtsi b/arch/loongarch/boot/dts/loongson-2k0500.dtsi
index 444779c21034..413b83366367 100644
--- a/arch/loongarch/boot/dts/loongson-2k0500.dtsi
+++ b/arch/loongarch/boot/dts/loongson-2k0500.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/loongson,ls2k-clk.h>
/ {
#address-cells = <2>;
@@ -19,14 +20,15 @@ cpu0: cpu@0 {
compatible = "loongson,la264";
device_type = "cpu";
reg = <0x0>;
- clocks = <&cpu_clk>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
};
};
- cpu_clk: cpu-clk {
+ ref_100m: clock-ref-100m {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <500000000>;
+ clock-frequency = <100000000>;
+ clock-output-names = "ref_100m";
};
cpuintc: interrupt-controller {
@@ -52,6 +54,55 @@ isa@16400000 {
ranges = <1 0x0 0x0 0x16400000 0x4000>;
};
+ clk: clock-controller@1fe10400 {
+ compatible = "loongson,ls2k0500-clk";
+ reg = <0x0 0x1fe10400 0x0 0x2c>;
+ #clock-cells = <1>;
+ clocks = <&ref_100m>;
+ clock-names = "ref_100m";
+ status = "disabled";
+ };
+
+ dma-controller@1fe10c00 {
+ compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
+ reg = <0 0x1fe10c00 0 0x8>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <67>;
+ clocks = <&clk LOONGSON2_APB_CLK>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
+
+ dma-controller@1fe10c10 {
+ compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
+ reg = <0 0x1fe10c10 0 0x8>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <68>;
+ clocks = <&clk LOONGSON2_APB_CLK>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
+
+ dma-controller@1fe10c20 {
+ compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
+ reg = <0 0x1fe10c20 0 0x8>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <69>;
+ clocks = <&clk LOONGSON2_APB_CLK>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
+
+ dma-controller@1fe10c30 {
+ compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
+ reg = <0 0x1fe10c30 0 0x8>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <70>;
+ clocks = <&clk LOONGSON2_APB_CLK>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
+
liointc0: interrupt-controller@1fe11400 {
compatible = "loongson,liointc-2.0";
reg = <0x0 0x1fe11400 0x0 0x40>,
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v1 8/8] LoongArch: dts: Add clock support to Loongson-2K2000
2024-03-26 9:00 [PATCH v1 0/8] Add Loongson-2k0500 and Loongson-2k2000 clock support Binbin Zhou
` (6 preceding siblings ...)
2024-03-26 9:01 ` [PATCH v1 7/8] LoongArch: dts: Add clock support to Loongson-2K0500 Binbin Zhou
@ 2024-03-26 9:01 ` Binbin Zhou
7 siblings, 0 replies; 14+ messages in thread
From: Binbin Zhou @ 2024-03-26 9:01 UTC (permalink / raw
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou
The module is supported, enable it.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
.../boot/dts/loongson-2k2000-ref.dts | 4 ++++
arch/loongarch/boot/dts/loongson-2k2000.dtsi | 19 +++++++++++++++----
2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/arch/loongarch/boot/dts/loongson-2k2000-ref.dts b/arch/loongarch/boot/dts/loongson-2k2000-ref.dts
index dca91caf895e..a7af345b30ea 100644
--- a/arch/loongarch/boot/dts/loongson-2k2000-ref.dts
+++ b/arch/loongarch/boot/dts/loongson-2k2000-ref.dts
@@ -39,6 +39,10 @@ linux,cma {
};
};
+&clk {
+ status = "okay";
+};
+
&sata {
status = "okay";
};
diff --git a/arch/loongarch/boot/dts/loongson-2k2000.dtsi b/arch/loongarch/boot/dts/loongson-2k2000.dtsi
index a231949b5f55..605efaba7292 100644
--- a/arch/loongarch/boot/dts/loongson-2k2000.dtsi
+++ b/arch/loongarch/boot/dts/loongson-2k2000.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/loongson,ls2k-clk.h>
/ {
#address-cells = <2>;
@@ -19,21 +20,22 @@ cpu0: cpu@1 {
compatible = "loongson,la364";
device_type = "cpu";
reg = <0x0>;
- clocks = <&cpu_clk>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
};
cpu1: cpu@2 {
compatible = "loongson,la364";
device_type = "cpu";
reg = <0x1>;
- clocks = <&cpu_clk>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
};
};
- cpu_clk: cpu-clk {
+ ref_100m: clock-ref-100m {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <1400000000>;
+ clock-frequency = <100000000>;
+ clock-output-names = "ref_100m";
};
cpuintc: interrupt-controller {
@@ -51,6 +53,15 @@ bus@10000000 {
#address-cells = <2>;
#size-cells = <2>;
+ clk: clock-controller@10010480 {
+ compatible = "loongson,ls2k2000-clk";
+ reg = <0x0 0x10010480 0x0 0x100>;
+ #clock-cells = <1>;
+ clocks = <&ref_100m>;
+ clock-names = "ref_100m";
+ status = "disabled";
+ };
+
pmc: power-management@100d0000 {
compatible = "loongson,ls2k2000-pmc", "loongson,ls2k0500-pmc", "syscon";
reg = <0x0 0x100d0000 0x0 0x58>;
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v1 1/8] dt-bindings: clock: add Loongson-2K expand clock index
2024-03-26 9:01 ` [PATCH v1 1/8] dt-bindings: clock: add Loongson-2K expand clock index Binbin Zhou
@ 2024-03-26 18:54 ` Conor Dooley
2024-03-27 1:15 ` Binbin Zhou
0 siblings, 1 reply; 14+ messages in thread
From: Conor Dooley @ 2024-03-26 18:54 UTC (permalink / raw
To: Binbin Zhou
Cc: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu,
Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch
[-- Attachment #1: Type: text/plain, Size: 268 bytes --]
On Tue, Mar 26, 2024 at 05:01:00PM +0800, Binbin Zhou wrote:
> -#define LOONGSON2_CLK_END 18
> +#define LOONGSON2_CLK_END 35
Please just delete this. If you can change it, it is not a binding.
Just define it in the driver if it is needed there.
Thanks,
Conor.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 3/8] dt-bindings: clock: loongson2: add Loongson-2K0500 compatible
2024-03-26 9:01 ` [PATCH v1 3/8] dt-bindings: clock: loongson2: add Loongson-2K0500 compatible Binbin Zhou
@ 2024-03-26 18:56 ` Conor Dooley
0 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2024-03-26 18:56 UTC (permalink / raw
To: Binbin Zhou
Cc: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu,
Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch
[-- Attachment #1: Type: text/plain, Size: 989 bytes --]
On Tue, Mar 26, 2024 at 05:01:02PM +0800, Binbin Zhou wrote:
> Add the devicetree compatible for Loongson-2K0500 clocks.
>
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> ---
> Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
> index 63a59015987e..83baee40e200 100644
> --- a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
> +++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
> @@ -16,7 +16,8 @@ description: |
> properties:
> compatible:
> enum:
> - - loongson,ls2k-clk
> + - loongson,ls2k0500-clk
> + - loongson,ls2k-clk # This is for Loongson-2K1000
Ah yes, the generic "ls2k" compatibles strike again :)
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 5/8] dt-bindings: clock: loongson2: add Loongson-2K2000 compatible
2024-03-26 9:01 ` [PATCH v1 5/8] dt-bindings: clock: loongson2: add Loongson-2K2000 compatible Binbin Zhou
@ 2024-03-26 18:56 ` Conor Dooley
0 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2024-03-26 18:56 UTC (permalink / raw
To: Binbin Zhou
Cc: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu,
Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch
[-- Attachment #1: Type: text/plain, Size: 882 bytes --]
On Tue, Mar 26, 2024 at 05:01:25PM +0800, Binbin Zhou wrote:
> Add the devicetree compatible for Loongson-2K2000 clocks.
>
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> ---
> Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
> index 83baee40e200..4f79cdb417ab 100644
> --- a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
> +++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
> @@ -18,6 +18,7 @@ properties:
> enum:
> - loongson,ls2k0500-clk
> - loongson,ls2k-clk # This is for Loongson-2K1000
> + - loongson,ls2k2000-clk
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 1/8] dt-bindings: clock: add Loongson-2K expand clock index
2024-03-26 18:54 ` Conor Dooley
@ 2024-03-27 1:15 ` Binbin Zhou
2024-03-27 16:55 ` Conor Dooley
0 siblings, 1 reply; 14+ messages in thread
From: Binbin Zhou @ 2024-03-27 1:15 UTC (permalink / raw
To: Conor Dooley
Cc: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu,
Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch
On Wed, Mar 27, 2024 at 12:54 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, Mar 26, 2024 at 05:01:00PM +0800, Binbin Zhou wrote:
>
> > -#define LOONGSON2_CLK_END 18
>
>
> > +#define LOONGSON2_CLK_END 35
>
> Please just delete this. If you can change it, it is not a binding.
> Just define it in the driver if it is needed there.
Hi Conor:
Ok, I will drop it in the next version.
Thanks.
Binbin
>
> Thanks,
> Conor.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 1/8] dt-bindings: clock: add Loongson-2K expand clock index
2024-03-27 1:15 ` Binbin Zhou
@ 2024-03-27 16:55 ` Conor Dooley
0 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2024-03-27 16:55 UTC (permalink / raw
To: Binbin Zhou
Cc: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu,
Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch
[-- Attachment #1: Type: text/plain, Size: 621 bytes --]
On Wed, Mar 27, 2024 at 07:15:40AM +0600, Binbin Zhou wrote:
> On Wed, Mar 27, 2024 at 12:54 AM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Tue, Mar 26, 2024 at 05:01:00PM +0800, Binbin Zhou wrote:
> >
> > > -#define LOONGSON2_CLK_END 18
> >
> >
> > > +#define LOONGSON2_CLK_END 35
> >
> > Please just delete this. If you can change it, it is not a binding.
> > Just define it in the driver if it is needed there.
>
> Hi Conor:
>
> Ok, I will drop it in the next version.
With that removed
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2024-03-27 16:55 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-03-26 9:00 [PATCH v1 0/8] Add Loongson-2k0500 and Loongson-2k2000 clock support Binbin Zhou
2024-03-26 9:01 ` [PATCH v1 1/8] dt-bindings: clock: add Loongson-2K expand clock index Binbin Zhou
2024-03-26 18:54 ` Conor Dooley
2024-03-27 1:15 ` Binbin Zhou
2024-03-27 16:55 ` Conor Dooley
2024-03-26 9:01 ` [PATCH v1 2/8] clk: clk-loongson2: Refactor driver for adding new platforms Binbin Zhou
2024-03-26 9:01 ` [PATCH v1 3/8] dt-bindings: clock: loongson2: add Loongson-2K0500 compatible Binbin Zhou
2024-03-26 18:56 ` Conor Dooley
2024-03-26 9:01 ` [PATCH v1 4/8] clk: clk-loongson2: Add Loongson-2K0500 clock support Binbin Zhou
2024-03-26 9:01 ` [PATCH v1 5/8] dt-bindings: clock: loongson2: add Loongson-2K2000 compatible Binbin Zhou
2024-03-26 18:56 ` Conor Dooley
2024-03-26 9:01 ` [PATCH v1 6/8] clk: clk-loongson2: Add Loongson-2K2000 clock support Binbin Zhou
2024-03-26 9:01 ` [PATCH v1 7/8] LoongArch: dts: Add clock support to Loongson-2K0500 Binbin Zhou
2024-03-26 9:01 ` [PATCH v1 8/8] LoongArch: dts: Add clock support to Loongson-2K2000 Binbin Zhou
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