From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Nathan Chancellor <nathan@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
Bill Wendling <morbo@google.com>,
Justin Stitt <justinstitt@google.com>,
"linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
linux-kernel@vger.kernel.org, llvm@lists.linux.dev,
Guenter Roeck <linux@roeck-us.net>
Subject: Re: [PATCH 6/8] MIPS: Limit MIPS_MT_SMP support by ISA reversion
Date: Wed, 15 May 2024 14:43:06 +0100 (BST) [thread overview]
Message-ID: <alpine.DEB.2.21.2405150850270.45291@angie.orcam.me.uk> (raw)
In-Reply-To: <7fc82f8b-df9d-45f5-8e82-27eac7b4b0ab@app.fastmail.com>
On Wed, 15 May 2024, Jiaxun Yang wrote:
> >> MIPS MT ASE is only available on ISA between Release 1 and Release 5.
> >
> > R2+ only actually, as also evident from Kconfig...
>
> Hi Maciej,
>
> Long time no see :-)
It's not so easy to get rid of me. ;)
> There is nothing stopping us to run R1 kernel on R2 hardware, given that
> those features are all detected at boot time. I understand MT was introduced
> at 34K which is R2.
We can certainly choose to support R2 features at run time with R1 kernel
configurations, but it's not what the change description says (left quoted
above for reference). And the MT ASE, indeed first implemented with the
34K (for which I was a member of the product development team back at MIPS
UK), is not a part of the R1 ISA specification set.
> >> --- a/arch/mips/Kconfig
> >> +++ b/arch/mips/Kconfig
> >> @@ -2171,7 +2171,8 @@ config CPU_R4K_CACHE_TLB
> >> config MIPS_MT_SMP
> >> bool "MIPS MT SMP support (1 TC on each available VPE)"
> >> default y
> >> - depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
> >> + depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6
> >> + depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS
> >> select CPU_MIPSR2_IRQ_VI
> >> select CPU_MIPSR2_IRQ_EI
> > ^^^^^^
> > ... here. I wish people looked beyond the line they change, sigh...
>
> Both features (VI and VEIC) are probed at boot time. Selecting
> them doesn't necessarily mean that CPU has those functions.
Both are optional for R2+, so necessarily they need to be probed for, but
they are not available in R1. The reverse dependency set here is another
indication that the MT ASE is an R2+ feature.
Maciej
next prev parent reply other threads:[~2024-05-15 13:43 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-02 18:21 [PATCH 0/8] MIPS: Aggregate build fixes Jiaxun Yang
2024-02-02 18:21 ` [PATCH 1/8] MIPS: Probe toolchain support of -msym32 Jiaxun Yang
2024-02-02 18:21 ` [PATCH 2/8] MIPS: Remove cc-option checks for -march=octeon Jiaxun Yang
2024-02-02 18:21 ` [PATCH 3/8] MIPS: Fallback CPU -march flag to ISA level if unsupported Jiaxun Yang
2024-02-02 18:21 ` [PATCH 4/8] MIPS: BMIPS: Drop unnecessary assembler flag Jiaxun Yang
2024-02-02 18:21 ` [PATCH 5/8] MIPS: Loongson64: test for -march=loongson3a cflag Jiaxun Yang
2024-02-02 18:21 ` [PATCH 6/8] MIPS: Limit MIPS_MT_SMP support by ISA reversion Jiaxun Yang
2024-05-14 21:38 ` Maciej W. Rozycki
2024-05-14 23:39 ` Jiaxun Yang
2024-05-15 13:43 ` Maciej W. Rozycki [this message]
2024-05-15 21:26 ` Jiaxun Yang
2024-05-16 22:44 ` Maciej W. Rozycki
2024-02-02 18:21 ` [PATCH 7/8] MIPS: Implement microMIPS MT ASE helpers Jiaxun Yang
2024-02-02 18:21 ` [PATCH 8/8] MIPS: mipsregs: Set proper ISA level for virt extensions Jiaxun Yang
2024-02-20 18:26 ` [PATCH 0/8] MIPS: Aggregate build fixes Jiaxun Yang
2024-02-23 9:18 ` Thomas Bogendoerfer
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