* [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata
@ 2024-02-14 17:55 Easwar Hariharan
2024-02-14 18:14 ` Mark Rutland
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Easwar Hariharan @ 2024-02-14 17:55 UTC (permalink / raw
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Marc Zyngier,
Rob Herring, Andre Przywara, Easwar Hariharan, Mark Rutland,
Oliver Upton, moderated list:ARM64 PORT (AARCH64 ARCHITECTURE),
open list:DOCUMENTATION, open list
Cc: stable
Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
suffers from all the same errata.
CC: stable@vger.kernel.org # 5.15+
Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
---
changelog:
v1->v2:
* v1: https://lore.kernel.org/linux-arm-kernel/20240212232909.2276378-1-eahariha@linux.microsoft.com/T/#u
* Consistently use MICROSOFT throughout
---
Documentation/arch/arm64/silicon-errata.rst | 7 +++++++
arch/arm64/include/asm/cputype.h | 4 ++++
arch/arm64/kernel/cpu_errata.c | 3 +++
3 files changed, 14 insertions(+)
diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index e8c2ce1f9df6..45a7f4932fe0 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -243,3 +243,10 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ASR | ASR8601 | #8601001 | N/A |
+----------------+-----------------+-----------------+-----------------------------+
++----------------+-----------------+-----------------+-----------------------------+
+| Microsoft | Azure Cobalt 100| #2139208 | ARM64_ERRATUM_2139208 |
++----------------+-----------------+-----------------+-----------------------------+
+| Microsoft | Azure Cobalt 100| #2067961 | ARM64_ERRATUM_2067961 |
++----------------+-----------------+-----------------+-----------------------------+
+| Microsoft | Azure Cobalt 100| #2253138 | ARM64_ERRATUM_2253138 |
++----------------+-----------------+-----------------+-----------------------------+
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 7c7493cb571f..52f076afeb96 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -61,6 +61,7 @@
#define ARM_CPU_IMP_HISI 0x48
#define ARM_CPU_IMP_APPLE 0x61
#define ARM_CPU_IMP_AMPERE 0xC0
+#define ARM_CPU_IMP_MICROSOFT 0x6D
#define ARM_CPU_PART_AEM_V8 0xD0F
#define ARM_CPU_PART_FOUNDATION 0xD00
@@ -135,6 +136,8 @@
#define AMPERE_CPU_PART_AMPERE1 0xAC3
+#define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */
+
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
@@ -193,6 +196,7 @@
#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
+#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)
/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 967c7c7a4e7d..76b8dd37092a 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -374,6 +374,7 @@ static const struct midr_range erratum_1463225[] = {
static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
#ifdef CONFIG_ARM64_ERRATUM_2139208
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
+ MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
#endif
#ifdef CONFIG_ARM64_ERRATUM_2119858
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
@@ -387,6 +388,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
static const struct midr_range tsb_flush_fail_cpus[] = {
#ifdef CONFIG_ARM64_ERRATUM_2067961
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
+ MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
#endif
#ifdef CONFIG_ARM64_ERRATUM_2054223
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
@@ -399,6 +401,7 @@ static const struct midr_range tsb_flush_fail_cpus[] = {
static struct midr_range trbe_write_out_of_range_cpus[] = {
#ifdef CONFIG_ARM64_ERRATUM_2253138
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
+ MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
#endif
#ifdef CONFIG_ARM64_ERRATUM_2224489
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata
2024-02-14 17:55 [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata Easwar Hariharan
@ 2024-02-14 18:14 ` Mark Rutland
2024-02-14 20:58 ` Oliver Upton
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Mark Rutland @ 2024-02-14 18:14 UTC (permalink / raw
To: Easwar Hariharan
Cc: Catalin Marinas, Will Deacon, Jonathan Corbet, Marc Zyngier,
Rob Herring, Andre Przywara, Oliver Upton,
moderated list:ARM64 PORT (AARCH64 ARCHITECTURE),
open list:DOCUMENTATION, open list, stable
On Wed, Feb 14, 2024 at 05:55:18PM +0000, Easwar Hariharan wrote:
> Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
> implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
> suffers from all the same errata.
>
> CC: stable@vger.kernel.org # 5.15+
> Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
I assume that Catalin/Will will take this through the arm64 tree.
Mark.
> ---
> changelog:
> v1->v2:
> * v1: https://lore.kernel.org/linux-arm-kernel/20240212232909.2276378-1-eahariha@linux.microsoft.com/T/#u
> * Consistently use MICROSOFT throughout
> ---
> Documentation/arch/arm64/silicon-errata.rst | 7 +++++++
> arch/arm64/include/asm/cputype.h | 4 ++++
> arch/arm64/kernel/cpu_errata.c | 3 +++
> 3 files changed, 14 insertions(+)
>
> diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
> index e8c2ce1f9df6..45a7f4932fe0 100644
> --- a/Documentation/arch/arm64/silicon-errata.rst
> +++ b/Documentation/arch/arm64/silicon-errata.rst
> @@ -243,3 +243,10 @@ stable kernels.
> +----------------+-----------------+-----------------+-----------------------------+
> | ASR | ASR8601 | #8601001 | N/A |
> +----------------+-----------------+-----------------+-----------------------------+
> ++----------------+-----------------+-----------------+-----------------------------+
> +| Microsoft | Azure Cobalt 100| #2139208 | ARM64_ERRATUM_2139208 |
> ++----------------+-----------------+-----------------+-----------------------------+
> +| Microsoft | Azure Cobalt 100| #2067961 | ARM64_ERRATUM_2067961 |
> ++----------------+-----------------+-----------------+-----------------------------+
> +| Microsoft | Azure Cobalt 100| #2253138 | ARM64_ERRATUM_2253138 |
> ++----------------+-----------------+-----------------+-----------------------------+
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index 7c7493cb571f..52f076afeb96 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -61,6 +61,7 @@
> #define ARM_CPU_IMP_HISI 0x48
> #define ARM_CPU_IMP_APPLE 0x61
> #define ARM_CPU_IMP_AMPERE 0xC0
> +#define ARM_CPU_IMP_MICROSOFT 0x6D
>
> #define ARM_CPU_PART_AEM_V8 0xD0F
> #define ARM_CPU_PART_FOUNDATION 0xD00
> @@ -135,6 +136,8 @@
>
> #define AMPERE_CPU_PART_AMPERE1 0xAC3
>
> +#define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */
> +
> #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
> #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
> #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
> @@ -193,6 +196,7 @@
> #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
> #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
> #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
> +#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)
>
> /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
> #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 967c7c7a4e7d..76b8dd37092a 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -374,6 +374,7 @@ static const struct midr_range erratum_1463225[] = {
> static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
> #ifdef CONFIG_ARM64_ERRATUM_2139208
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
> #endif
> #ifdef CONFIG_ARM64_ERRATUM_2119858
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> @@ -387,6 +388,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
> static const struct midr_range tsb_flush_fail_cpus[] = {
> #ifdef CONFIG_ARM64_ERRATUM_2067961
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
> #endif
> #ifdef CONFIG_ARM64_ERRATUM_2054223
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> @@ -399,6 +401,7 @@ static const struct midr_range tsb_flush_fail_cpus[] = {
> static struct midr_range trbe_write_out_of_range_cpus[] = {
> #ifdef CONFIG_ARM64_ERRATUM_2253138
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
> #endif
> #ifdef CONFIG_ARM64_ERRATUM_2224489
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata
2024-02-14 17:55 [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata Easwar Hariharan
2024-02-14 18:14 ` Mark Rutland
@ 2024-02-14 20:58 ` Oliver Upton
2024-02-15 6:52 ` Anshuman Khandual
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Oliver Upton @ 2024-02-14 20:58 UTC (permalink / raw
To: Easwar Hariharan
Cc: Catalin Marinas, Will Deacon, Jonathan Corbet, Marc Zyngier,
Rob Herring, Andre Przywara, Mark Rutland,
moderated list:ARM64 PORT (AARCH64 ARCHITECTURE),
open list:DOCUMENTATION, open list, stable
On Wed, Feb 14, 2024 at 05:55:18PM +0000, Easwar Hariharan wrote:
> Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
> implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
> suffers from all the same errata.
>
> CC: stable@vger.kernel.org # 5.15+
> Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
--
Thanks,
Oliver
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata
2024-02-14 17:55 [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata Easwar Hariharan
2024-02-14 18:14 ` Mark Rutland
2024-02-14 20:58 ` Oliver Upton
@ 2024-02-15 6:52 ` Anshuman Khandual
2024-02-15 9:57 ` Marc Zyngier
2024-02-15 12:44 ` Will Deacon
4 siblings, 0 replies; 6+ messages in thread
From: Anshuman Khandual @ 2024-02-15 6:52 UTC (permalink / raw
To: Easwar Hariharan, Catalin Marinas, Will Deacon, Jonathan Corbet,
Marc Zyngier, Rob Herring, Andre Przywara, Mark Rutland,
Oliver Upton, moderated list:ARM64 PORT (AARCH64 ARCHITECTURE),
open list:DOCUMENTATION, open list
Cc: stable
On 2/14/24 23:25, Easwar Hariharan wrote:
> Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
> implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
> suffers from all the same errata.
>
> CC: stable@vger.kernel.org # 5.15+
> Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> changelog:
> v1->v2:
> * v1: https://lore.kernel.org/linux-arm-kernel/20240212232909.2276378-1-eahariha@linux.microsoft.com/T/#u
> * Consistently use MICROSOFT throughout
> ---
> Documentation/arch/arm64/silicon-errata.rst | 7 +++++++
> arch/arm64/include/asm/cputype.h | 4 ++++
> arch/arm64/kernel/cpu_errata.c | 3 +++
> 3 files changed, 14 insertions(+)
>
> diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
> index e8c2ce1f9df6..45a7f4932fe0 100644
> --- a/Documentation/arch/arm64/silicon-errata.rst
> +++ b/Documentation/arch/arm64/silicon-errata.rst
> @@ -243,3 +243,10 @@ stable kernels.
> +----------------+-----------------+-----------------+-----------------------------+
> | ASR | ASR8601 | #8601001 | N/A |
> +----------------+-----------------+-----------------+-----------------------------+
> ++----------------+-----------------+-----------------+-----------------------------+
> +| Microsoft | Azure Cobalt 100| #2139208 | ARM64_ERRATUM_2139208 |
> ++----------------+-----------------+-----------------+-----------------------------+
> +| Microsoft | Azure Cobalt 100| #2067961 | ARM64_ERRATUM_2067961 |
> ++----------------+-----------------+-----------------+-----------------------------+
> +| Microsoft | Azure Cobalt 100| #2253138 | ARM64_ERRATUM_2253138 |
> ++----------------+-----------------+-----------------+-----------------------------+
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index 7c7493cb571f..52f076afeb96 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -61,6 +61,7 @@
> #define ARM_CPU_IMP_HISI 0x48
> #define ARM_CPU_IMP_APPLE 0x61
> #define ARM_CPU_IMP_AMPERE 0xC0
> +#define ARM_CPU_IMP_MICROSOFT 0x6D
>
> #define ARM_CPU_PART_AEM_V8 0xD0F
> #define ARM_CPU_PART_FOUNDATION 0xD00
> @@ -135,6 +136,8 @@
>
> #define AMPERE_CPU_PART_AMPERE1 0xAC3
>
> +#define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */
> +
> #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
> #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
> #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
> @@ -193,6 +196,7 @@
> #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
> #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
> #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
> +#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)
>
> /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
> #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 967c7c7a4e7d..76b8dd37092a 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -374,6 +374,7 @@ static const struct midr_range erratum_1463225[] = {
> static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
> #ifdef CONFIG_ARM64_ERRATUM_2139208
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
> #endif
> #ifdef CONFIG_ARM64_ERRATUM_2119858
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> @@ -387,6 +388,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
> static const struct midr_range tsb_flush_fail_cpus[] = {
> #ifdef CONFIG_ARM64_ERRATUM_2067961
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
> #endif
> #ifdef CONFIG_ARM64_ERRATUM_2054223
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> @@ -399,6 +401,7 @@ static const struct midr_range tsb_flush_fail_cpus[] = {
> static struct midr_range trbe_write_out_of_range_cpus[] = {
> #ifdef CONFIG_ARM64_ERRATUM_2253138
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
> #endif
> #ifdef CONFIG_ARM64_ERRATUM_2224489
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata
2024-02-14 17:55 [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata Easwar Hariharan
` (2 preceding siblings ...)
2024-02-15 6:52 ` Anshuman Khandual
@ 2024-02-15 9:57 ` Marc Zyngier
2024-02-15 12:44 ` Will Deacon
4 siblings, 0 replies; 6+ messages in thread
From: Marc Zyngier @ 2024-02-15 9:57 UTC (permalink / raw
To: Easwar Hariharan
Cc: Catalin Marinas, Will Deacon, Jonathan Corbet, Rob Herring,
Andre Przywara, Mark Rutland, Oliver Upton,
moderated list:ARM64 PORT (AARCH64 ARCHITECTURE),
open list:DOCUMENTATION, open list, stable
On Wed, 14 Feb 2024 17:55:18 +0000,
Easwar Hariharan <eahariha@linux.microsoft.com> wrote:
>
> Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
> implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
> suffers from all the same errata.
>
> CC: stable@vger.kernel.org # 5.15+
> Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
Thanks for respinning this.
Acked-by: Marc Zyngier <maz@kernel.org>
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata
2024-02-14 17:55 [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata Easwar Hariharan
` (3 preceding siblings ...)
2024-02-15 9:57 ` Marc Zyngier
@ 2024-02-15 12:44 ` Will Deacon
4 siblings, 0 replies; 6+ messages in thread
From: Will Deacon @ 2024-02-15 12:44 UTC (permalink / raw
To: Marc Zyngier, Mark Rutland, Easwar Hariharan, Catalin Marinas,
open list:DOCUMENTATION, open list, Oliver Upton, Rob Herring,
moderated list:ARM64 PORT AARCH64 ARCHITECTURE, Jonathan Corbet,
Andre Przywara
Cc: kernel-team, Will Deacon, stable
On Wed, 14 Feb 2024 17:55:18 +0000, Easwar Hariharan wrote:
> Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
> implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
> suffers from all the same errata.
>
>
Applied to arm64 (for-next/fixes), thanks!
[1/1] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata
https://git.kernel.org/arm64/c/fb091ff39479
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-02-15 12:44 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2024-02-14 17:55 [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata Easwar Hariharan
2024-02-14 18:14 ` Mark Rutland
2024-02-14 20:58 ` Oliver Upton
2024-02-15 6:52 ` Anshuman Khandual
2024-02-15 9:57 ` Marc Zyngier
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