* [PATCH v4 0/8] riscv: dts: starfive: add Milkv Mars board device tree
@ 2024-04-29 0:13 Jisheng Zhang
2024-04-29 0:13 ` [PATCH v4 1/8] riscv: dts: starfive: add 'cpus' label to jh7110 and jh7100 soc dtsi Jisheng Zhang
` (8 more replies)
0 siblings, 9 replies; 14+ messages in thread
From: Jisheng Zhang @ 2024-04-29 0:13 UTC (permalink / raw
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-kernel
The Milkv Mars is a development board based on the Starfive JH7110 SoC.
The board features:
- JH7110 SoC
- 1/2/4/8 GiB LPDDR4 DRAM
- AXP15060 PMIC
- 40 pin GPIO header
- 3x USB 3.0 host port
- 1x USB 2.0 host port
- 1x M.2 E-Key
- 1x eMMC slot
- 1x MicroSD slot
- 1x QSPI Flash
- 1x 1Gbps Ethernet port
- 1x HDMI port
- 1x 2-lane DSI and 1x 4-lane DSI
- 1x 2-lane CSI
patch1 adds 'cpus' label
patch2 adds "milkv,mars" board dt-binding
patch3 ~ patch4 adopt Krzysztof's suggestions to DT node names
patch5 introduces a board common dtsi for visionfive2 and mars
patch3 adds the mars board dts file describing the currently supported
features:
Namely PMIC, UART, I2C, GPIO, SD card, QSPI Flash, eMMC and Ethernet.
Since v3:
- collect Reviewed-by tag
- rename the common dtsi to jh7110-common.dtsi
- mv cd-gpios and disable-wp into jh7110-common.dtsi
- fix "gmac1-rgmii-rxin-clock: 'clock-frequency' is a required property"
warning
Since v2:
- add a common board file which can be used by vf2 and mars
Since v1:
- add two new patches which add "cpus" label and board dt-binding
- adopt Krzysztof's suggestions, thanks
Jisheng Zhang (8):
riscv: dts: starfive: add 'cpus' label to jh7110 and jh7100 soc dtsi
dt-bindings: riscv: starfive: add Milkv Mars board
riscv: dts: starfive: visionfive 2: update sound and codec dt node
name
riscv: dts: starfive: visionfive 2: use cpus label for timebase freq
riscv: dts: starfive: visionfive 2: add tf cd-gpios
riscv: dts: starfive: visionfive 2: add "disable-wp" for tfcard
riscv: dts: starfive: introduce a common board dtsi for jh7110 based
boards
riscv: dts: starfive: add Milkv Mars board device tree
.../devicetree/bindings/riscv/starfive.yaml | 1 +
arch/riscv/boot/dts/starfive/Makefile | 1 +
arch/riscv/boot/dts/starfive/jh7100.dtsi | 2 +-
.../boot/dts/starfive/jh7110-common.dtsi | 599 ++++++++++++++++++
.../boot/dts/starfive/jh7110-milkv-mars.dts | 30 +
.../jh7110-starfive-visionfive-2.dtsi | 584 +----------------
arch/riscv/boot/dts/starfive/jh7110.dtsi | 2 +-
7 files changed, 634 insertions(+), 585 deletions(-)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-common.dtsi
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
--
2.43.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 1/8] riscv: dts: starfive: add 'cpus' label to jh7110 and jh7100 soc dtsi
2024-04-29 0:13 [PATCH v4 0/8] riscv: dts: starfive: add Milkv Mars board device tree Jisheng Zhang
@ 2024-04-29 0:13 ` Jisheng Zhang
2024-04-29 0:13 ` [PATCH v4 2/8] dt-bindings: riscv: starfive: add Milkv Mars board Jisheng Zhang
` (7 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Jisheng Zhang @ 2024-04-29 0:13 UTC (permalink / raw
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-kernel, Emil Renner Berthing
Add the 'cpus' label so that we can reference it in board dts files.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
arch/riscv/boot/dts/starfive/jh7100.dtsi | 2 +-
arch/riscv/boot/dts/starfive/jh7110.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 9a2e9583af88..7de0732b8eab 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -13,7 +13,7 @@ / {
#address-cells = <2>;
#size-cells = <2>;
- cpus {
+ cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4a5708f7fcf7..18047195c600 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -15,7 +15,7 @@ / {
#address-cells = <2>;
#size-cells = <2>;
- cpus {
+ cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 2/8] dt-bindings: riscv: starfive: add Milkv Mars board
2024-04-29 0:13 [PATCH v4 0/8] riscv: dts: starfive: add Milkv Mars board device tree Jisheng Zhang
2024-04-29 0:13 ` [PATCH v4 1/8] riscv: dts: starfive: add 'cpus' label to jh7110 and jh7100 soc dtsi Jisheng Zhang
@ 2024-04-29 0:13 ` Jisheng Zhang
2024-04-29 0:13 ` [PATCH v4 3/8] riscv: dts: starfive: visionfive 2: update sound and codec dt node name Jisheng Zhang
` (6 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Jisheng Zhang @ 2024-04-29 0:13 UTC (permalink / raw
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-kernel, Krzysztof Kozlowski,
Emil Renner Berthing
Add device tree bindings for the Milkv Mars board which is
equipped with StarFive JH7110 SoC.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
Documentation/devicetree/bindings/riscv/starfive.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index cc4d92f0a1bf..b672f8521949 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -26,6 +26,7 @@ properties:
- items:
- enum:
+ - milkv,mars
- starfive,visionfive-2-v1.2a
- starfive,visionfive-2-v1.3b
- const: starfive,jh7110
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 3/8] riscv: dts: starfive: visionfive 2: update sound and codec dt node name
2024-04-29 0:13 [PATCH v4 0/8] riscv: dts: starfive: add Milkv Mars board device tree Jisheng Zhang
2024-04-29 0:13 ` [PATCH v4 1/8] riscv: dts: starfive: add 'cpus' label to jh7110 and jh7100 soc dtsi Jisheng Zhang
2024-04-29 0:13 ` [PATCH v4 2/8] dt-bindings: riscv: starfive: add Milkv Mars board Jisheng Zhang
@ 2024-04-29 0:13 ` Jisheng Zhang
2024-04-29 0:13 ` [PATCH v4 4/8] riscv: dts: starfive: visionfive 2: use cpus label for timebase freq Jisheng Zhang
` (5 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Jisheng Zhang @ 2024-04-29 0:13 UTC (permalink / raw
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-kernel, Krzysztof Kozlowski,
Emil Renner Berthing
Use "audio-codec" as the codec dt node name, and "sound" as the simple
audio card dt name.
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
.../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index ccd0ce55aa53..50955cc45658 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -41,12 +41,12 @@ gpio-restart {
priority = <224>;
};
- pwmdac_codec: pwmdac-codec {
+ pwmdac_codec: audio-codec {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
- sound-pwmdac {
+ sound {
compatible = "simple-audio-card";
simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
#address-cells = <1>;
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 4/8] riscv: dts: starfive: visionfive 2: use cpus label for timebase freq
2024-04-29 0:13 [PATCH v4 0/8] riscv: dts: starfive: add Milkv Mars board device tree Jisheng Zhang
` (2 preceding siblings ...)
2024-04-29 0:13 ` [PATCH v4 3/8] riscv: dts: starfive: visionfive 2: update sound and codec dt node name Jisheng Zhang
@ 2024-04-29 0:13 ` Jisheng Zhang
2024-04-29 0:13 ` [PATCH v4 5/8] riscv: dts: starfive: visionfive 2: add tf cd-gpios Jisheng Zhang
` (4 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Jisheng Zhang @ 2024-04-29 0:13 UTC (permalink / raw
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-kernel, Krzysztof Kozlowski,
Emil Renner Berthing
As pointed out by Krzysztof "Board should not bring new CPU nodes.
Override by label instead."
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
.../boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 50955cc45658..910c07bd4af9 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -26,10 +26,6 @@ chosen {
stdout-path = "serial0:115200n8";
};
- cpus {
- timebase-frequency = <4000000>;
- };
-
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x1 0x0>;
@@ -69,6 +65,10 @@ codec {
};
};
+&cpus {
+ timebase-frequency = <4000000>;
+};
+
&dvp_clk {
clock-frequency = <74250000>;
};
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 5/8] riscv: dts: starfive: visionfive 2: add tf cd-gpios
2024-04-29 0:13 [PATCH v4 0/8] riscv: dts: starfive: add Milkv Mars board device tree Jisheng Zhang
` (3 preceding siblings ...)
2024-04-29 0:13 ` [PATCH v4 4/8] riscv: dts: starfive: visionfive 2: use cpus label for timebase freq Jisheng Zhang
@ 2024-04-29 0:13 ` Jisheng Zhang
2024-04-29 13:46 ` Emil Renner Berthing
2024-04-29 0:13 ` [PATCH v4 6/8] riscv: dts: starfive: visionfive 2: add "disable-wp" for tfcard Jisheng Zhang
` (3 subsequent siblings)
8 siblings, 1 reply; 14+ messages in thread
From: Jisheng Zhang @ 2024-04-29 0:13 UTC (permalink / raw
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-kernel
Per VisionFive 2 1.2B, and 1.3A boards' SCH, GPIO 41 is used as
card detect. So add "cd-gpios" property for this.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 910c07bd4af9..b6030d63459d 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -303,7 +303,7 @@ &mmc1 {
bus-width = <4>;
no-sdio;
no-mmc;
- broken-cd;
+ cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
cap-sd-highspeed;
post-power-on-delay-ms = <200>;
pinctrl-names = "default";
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 6/8] riscv: dts: starfive: visionfive 2: add "disable-wp" for tfcard
2024-04-29 0:13 [PATCH v4 0/8] riscv: dts: starfive: add Milkv Mars board device tree Jisheng Zhang
` (4 preceding siblings ...)
2024-04-29 0:13 ` [PATCH v4 5/8] riscv: dts: starfive: visionfive 2: add tf cd-gpios Jisheng Zhang
@ 2024-04-29 0:13 ` Jisheng Zhang
2024-04-29 13:47 ` Emil Renner Berthing
2024-04-29 0:13 ` [PATCH v4 7/8] riscv: dts: starfive: introduce a common board dtsi for jh7110 based boards Jisheng Zhang
` (2 subsequent siblings)
8 siblings, 1 reply; 14+ messages in thread
From: Jisheng Zhang @ 2024-04-29 0:13 UTC (permalink / raw
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-kernel
No physical write-protect line is present, so setting "disable-wp".
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index b6030d63459d..e19f26628054 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -304,6 +304,7 @@ &mmc1 {
no-sdio;
no-mmc;
cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+ disable-wp;
cap-sd-highspeed;
post-power-on-delay-ms = <200>;
pinctrl-names = "default";
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 7/8] riscv: dts: starfive: introduce a common board dtsi for jh7110 based boards
2024-04-29 0:13 [PATCH v4 0/8] riscv: dts: starfive: add Milkv Mars board device tree Jisheng Zhang
` (5 preceding siblings ...)
2024-04-29 0:13 ` [PATCH v4 6/8] riscv: dts: starfive: visionfive 2: add "disable-wp" for tfcard Jisheng Zhang
@ 2024-04-29 0:13 ` Jisheng Zhang
2024-04-29 13:51 ` Emil Renner Berthing
2024-04-29 0:13 ` [PATCH v4 8/8] riscv: dts: starfive: add Milkv Mars board device tree Jisheng Zhang
2024-04-30 21:20 ` [PATCH v4 0/8] " Conor Dooley
8 siblings, 1 reply; 14+ messages in thread
From: Jisheng Zhang @ 2024-04-29 0:13 UTC (permalink / raw
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-kernel
This is to prepare for Milkv Mars board dts support in the following
patch. Let's factored out common part into .dtsi.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
.../boot/dts/starfive/jh7110-common.dtsi | 599 ++++++++++++++++++
.../jh7110-starfive-visionfive-2.dtsi | 585 +----------------
2 files changed, 600 insertions(+), 584 deletions(-)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-common.dtsi
diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
new file mode 100644
index 000000000000..8ff6ea64f048
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -0,0 +1,599 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include "jh7110.dtsi"
+#include "jh7110-pinfunc.h"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ ethernet0 = &gmac0;
+ i2c0 = &i2c0;
+ i2c2 = &i2c2;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x1 0x0>;
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
+ priority = <224>;
+ };
+
+ pwmdac_codec: audio-codec {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ simple-audio-card,dai-link@0 {
+ reg = <0>;
+ format = "left_j";
+ bitclock-master = <&sndcpu0>;
+ frame-master = <&sndcpu0>;
+
+ sndcpu0: cpu {
+ sound-dai = <&pwmdac>;
+ };
+
+ codec {
+ sound-dai = <&pwmdac_codec>;
+ };
+ };
+ };
+};
+
+&cpus {
+ timebase-frequency = <4000000>;
+};
+
+&dvp_clk {
+ clock-frequency = <74250000>;
+};
+
+&gmac0_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&gmac0_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&gmac1_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&gmac1_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&hdmitx0_pixelclk {
+ clock-frequency = <297000000>;
+};
+
+&i2srx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2srx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&i2stx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2stx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&mclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&osc {
+ clock-frequency = <24000000>;
+};
+
+&rtc_osc {
+ clock-frequency = <32768>;
+};
+
+&tdm_ext {
+ clock-frequency = <49152000>;
+};
+
+&camss {
+ assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
+ <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
+ assigned-clock-rates = <49500000>, <198000000>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ camss_from_csi2rx: endpoint {
+ remote-endpoint = <&csi2rx_to_camss>;
+ };
+ };
+ };
+};
+
+&csi2rx {
+ assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
+ assigned-clock-rates = <297000000>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ /* remote MIPI sensor endpoint */
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csi2rx_to_camss: endpoint {
+ remote-endpoint = <&camss_from_csi2rx>;
+ };
+ };
+ };
+};
+
+&gmac0 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+};
+
+&i2c5 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ status = "okay";
+
+ axp15060: pmic@36 {
+ compatible = "x-powers,axp15060";
+ reg = <0x36>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ regulators {
+ vcc_3v3: dcdc1 {
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3";
+ };
+
+ vdd_cpu: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1540000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ emmc_vdd: aldo4 {
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "emmc_vdd";
+ };
+ };
+ };
+};
+
+&i2c6 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pins>;
+ status = "okay";
+};
+
+&mmc0 {
+ max-frequency = <100000000>;
+ assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
+ assigned-clock-rates = <50000000>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ post-power-on-delay-ms = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&emmc_vdd>;
+ status = "okay";
+};
+
+&mmc1 {
+ max-frequency = <100000000>;
+ assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
+ assigned-clock-rates = <50000000>;
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+ cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ cap-sd-highspeed;
+ post-power-on-delay-ms = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ status = "okay";
+};
+
+&pwmdac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwmdac_pins>;
+ status = "okay";
+};
+
+&qspi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ nor_flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ cdns,read-delay = <5>;
+ spi-max-frequency = <12000000>;
+ cdns,tshsl-ns = <1>;
+ cdns,tsd2d-ns = <1>;
+ cdns,tchsh-ns = <1>;
+ cdns,tslch-ns = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spl@0 {
+ reg = <0x0 0x80000>;
+ };
+ uboot-env@f0000 {
+ reg = <0xf0000 0x10000>;
+ };
+ uboot@100000 {
+ reg = <0x100000 0x400000>;
+ };
+ reserved-data@600000 {
+ reg = <0x600000 0xa00000>;
+ };
+ };
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ status = "okay";
+
+ spi_dev0: spi@0 {
+ compatible = "rohm,dh2228fv";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
+&sysgpio {
+ i2c0_pins: i2c0-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(57, GPOUT_LOW,
+ GPOEN_SYS_I2C0_CLK,
+ GPI_SYS_I2C0_CLK)>,
+ <GPIOMUX(58, GPOUT_LOW,
+ GPOEN_SYS_I2C0_DATA,
+ GPI_SYS_I2C0_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ i2c2_pins: i2c2-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(3, GPOUT_LOW,
+ GPOEN_SYS_I2C2_CLK,
+ GPI_SYS_I2C2_CLK)>,
+ <GPIOMUX(2, GPOUT_LOW,
+ GPOEN_SYS_I2C2_DATA,
+ GPI_SYS_I2C2_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ i2c5_pins: i2c5-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(19, GPOUT_LOW,
+ GPOEN_SYS_I2C5_CLK,
+ GPI_SYS_I2C5_CLK)>,
+ <GPIOMUX(20, GPOUT_LOW,
+ GPOEN_SYS_I2C5_DATA,
+ GPI_SYS_I2C5_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ i2c6_pins: i2c6-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(16, GPOUT_LOW,
+ GPOEN_SYS_I2C6_CLK,
+ GPI_SYS_I2C6_CLK)>,
+ <GPIOMUX(17, GPOUT_LOW,
+ GPOEN_SYS_I2C6_DATA,
+ GPI_SYS_I2C6_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ mmc0_pins: mmc0-0 {
+ rst-pins {
+ pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ mmc-pins {
+ pinmux = <PINMUX(64, 0)>,
+ <PINMUX(65, 0)>,
+ <PINMUX(66, 0)>,
+ <PINMUX(67, 0)>,
+ <PINMUX(68, 0)>,
+ <PINMUX(69, 0)>,
+ <PINMUX(70, 0)>,
+ <PINMUX(71, 0)>,
+ <PINMUX(72, 0)>,
+ <PINMUX(73, 0)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ };
+ };
+
+ mmc1_pins: mmc1-0 {
+ clk-pins {
+ pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ mmc-pins {
+ pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
+ GPOEN_SYS_SDIO1_CMD,
+ GPI_SYS_SDIO1_CMD)>,
+ <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
+ GPOEN_SYS_SDIO1_DATA0,
+ GPI_SYS_SDIO1_DATA0)>,
+ <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
+ GPOEN_SYS_SDIO1_DATA1,
+ GPI_SYS_SDIO1_DATA1)>,
+ <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
+ GPOEN_SYS_SDIO1_DATA2,
+ GPI_SYS_SDIO1_DATA2)>,
+ <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
+ GPOEN_SYS_SDIO1_DATA3,
+ GPI_SYS_SDIO1_DATA3)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+
+ pwmdac_pins: pwmdac-0 {
+ pwmdac-pins {
+ pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
+ GPOEN_ENABLE,
+ GPI_NONE)>,
+ <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <2>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm_pins: pwm-0 {
+ pwm-pins {
+ pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
+ GPOEN_SYS_PWM0_CHANNEL0,
+ GPI_NONE)>,
+ <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
+ GPOEN_SYS_PWM0_CHANNEL1,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ spi0_pins: spi0-0 {
+ mosi-pins {
+ pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-disable;
+ input-disable;
+ input-schmitt-disable;
+ };
+
+ miso-pins {
+ pinmux = <GPIOMUX(53, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_SPI0_RXD)>;
+ bias-pull-up;
+ input-enable;
+ input-schmitt-enable;
+ };
+
+ sck-pins {
+ pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
+ GPOEN_ENABLE,
+ GPI_SYS_SPI0_CLK)>;
+ bias-disable;
+ input-disable;
+ input-schmitt-disable;
+ };
+
+ ss-pins {
+ pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
+ GPOEN_ENABLE,
+ GPI_SYS_SPI0_FSS)>;
+ bias-disable;
+ input-disable;
+ input-schmitt-disable;
+ };
+ };
+
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pinmux = <GPIOMUX(6, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_UART0_RX)>;
+ bias-disable; /* external pull-up */
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&U74_1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_4 {
+ cpu-supply = <&vdd_cpu>;
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index e19f26628054..9d70f21c86fc 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -5,188 +5,11 @@
*/
/dts-v1/;
-#include "jh7110.dtsi"
-#include "jh7110-pinfunc.h"
-#include <dt-bindings/gpio/gpio.h>
+#include "jh7110-common.dtsi"
/ {
aliases {
- ethernet0 = &gmac0;
ethernet1 = &gmac1;
- i2c0 = &i2c0;
- i2c2 = &i2c2;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- mmc0 = &mmc0;
- mmc1 = &mmc1;
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0x1 0x0>;
- };
-
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
- priority = <224>;
- };
-
- pwmdac_codec: audio-codec {
- compatible = "linux,spdif-dit";
- #sound-dai-cells = <0>;
- };
-
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
- #address-cells = <1>;
- #size-cells = <0>;
-
- simple-audio-card,dai-link@0 {
- reg = <0>;
- format = "left_j";
- bitclock-master = <&sndcpu0>;
- frame-master = <&sndcpu0>;
-
- sndcpu0: cpu {
- sound-dai = <&pwmdac>;
- };
-
- codec {
- sound-dai = <&pwmdac_codec>;
- };
- };
- };
-};
-
-&cpus {
- timebase-frequency = <4000000>;
-};
-
-&dvp_clk {
- clock-frequency = <74250000>;
-};
-
-&gmac0_rgmii_rxin {
- clock-frequency = <125000000>;
-};
-
-&gmac0_rmii_refin {
- clock-frequency = <50000000>;
-};
-
-&gmac1_rgmii_rxin {
- clock-frequency = <125000000>;
-};
-
-&gmac1_rmii_refin {
- clock-frequency = <50000000>;
-};
-
-&hdmitx0_pixelclk {
- clock-frequency = <297000000>;
-};
-
-&i2srx_bclk_ext {
- clock-frequency = <12288000>;
-};
-
-&i2srx_lrck_ext {
- clock-frequency = <192000>;
-};
-
-&i2stx_bclk_ext {
- clock-frequency = <12288000>;
-};
-
-&i2stx_lrck_ext {
- clock-frequency = <192000>;
-};
-
-&mclk_ext {
- clock-frequency = <12288000>;
-};
-
-&osc {
- clock-frequency = <24000000>;
-};
-
-&rtc_osc {
- clock-frequency = <32768>;
-};
-
-&tdm_ext {
- clock-frequency = <49152000>;
-};
-
-&camss {
- assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
- <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
- assigned-clock-rates = <49500000>, <198000000>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- reg = <1>;
-
- camss_from_csi2rx: endpoint {
- remote-endpoint = <&csi2rx_to_camss>;
- };
- };
- };
-};
-
-&csi2rx {
- assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
- assigned-clock-rates = <297000000>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- /* remote MIPI sensor endpoint */
- };
-
- port@1 {
- reg = <1>;
-
- csi2rx_to_camss: endpoint {
- remote-endpoint = <&camss_from_csi2rx>;
- };
- };
- };
-};
-
-&gmac0 {
- phy-handle = <&phy0>;
- phy-mode = "rgmii-id";
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
-
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
};
};
@@ -206,412 +29,6 @@ phy1: ethernet-phy@1 {
};
};
-&i2c0 {
- clock-frequency = <100000>;
- i2c-sda-hold-time-ns = <300>;
- i2c-sda-falling-time-ns = <510>;
- i2c-scl-falling-time-ns = <510>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- status = "okay";
-};
-
-&i2c2 {
- clock-frequency = <100000>;
- i2c-sda-hold-time-ns = <300>;
- i2c-sda-falling-time-ns = <510>;
- i2c-scl-falling-time-ns = <510>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
- status = "okay";
-};
-
-&i2c5 {
- clock-frequency = <100000>;
- i2c-sda-hold-time-ns = <300>;
- i2c-sda-falling-time-ns = <510>;
- i2c-scl-falling-time-ns = <510>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_pins>;
- status = "okay";
-
- axp15060: pmic@36 {
- compatible = "x-powers,axp15060";
- reg = <0x36>;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- regulators {
- vcc_3v3: dcdc1 {
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_3v3";
- };
-
- vdd_cpu: dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1540000>;
- regulator-name = "vdd-cpu";
- };
-
- emmc_vdd: aldo4 {
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "emmc_vdd";
- };
- };
- };
-};
-
-&i2c6 {
- clock-frequency = <100000>;
- i2c-sda-hold-time-ns = <300>;
- i2c-sda-falling-time-ns = <510>;
- i2c-scl-falling-time-ns = <510>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c6_pins>;
- status = "okay";
-};
-
&mmc0 {
- max-frequency = <100000000>;
- assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
- assigned-clock-rates = <50000000>;
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
non-removable;
- cap-mmc-hw-reset;
- post-power-on-delay-ms = <200>;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&emmc_vdd>;
- status = "okay";
-};
-
-&mmc1 {
- max-frequency = <100000000>;
- assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
- assigned-clock-rates = <50000000>;
- bus-width = <4>;
- no-sdio;
- no-mmc;
- cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
- disable-wp;
- cap-sd-highspeed;
- post-power-on-delay-ms = <200>;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins>;
- status = "okay";
-};
-
-&pwmdac {
- pinctrl-names = "default";
- pinctrl-0 = <&pwmdac_pins>;
- status = "okay";
-};
-
-&qspi {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- nor_flash: flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- cdns,read-delay = <5>;
- spi-max-frequency = <12000000>;
- cdns,tshsl-ns = <1>;
- cdns,tsd2d-ns = <1>;
- cdns,tchsh-ns = <1>;
- cdns,tslch-ns = <1>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- spl@0 {
- reg = <0x0 0x80000>;
- };
- uboot-env@f0000 {
- reg = <0xf0000 0x10000>;
- };
- uboot@100000 {
- reg = <0x100000 0x400000>;
- };
- reserved-data@600000 {
- reg = <0x600000 0xa00000>;
- };
- };
- };
-};
-
-&pwm {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm_pins>;
- status = "okay";
-};
-
-&spi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_pins>;
- status = "okay";
-
- spi_dev0: spi@0 {
- compatible = "rohm,dh2228fv";
- reg = <0>;
- spi-max-frequency = <10000000>;
- };
-};
-
-&sysgpio {
- i2c0_pins: i2c0-0 {
- i2c-pins {
- pinmux = <GPIOMUX(57, GPOUT_LOW,
- GPOEN_SYS_I2C0_CLK,
- GPI_SYS_I2C0_CLK)>,
- <GPIOMUX(58, GPOUT_LOW,
- GPOEN_SYS_I2C0_DATA,
- GPI_SYS_I2C0_DATA)>;
- bias-disable; /* external pull-up */
- input-enable;
- input-schmitt-enable;
- };
- };
-
- i2c2_pins: i2c2-0 {
- i2c-pins {
- pinmux = <GPIOMUX(3, GPOUT_LOW,
- GPOEN_SYS_I2C2_CLK,
- GPI_SYS_I2C2_CLK)>,
- <GPIOMUX(2, GPOUT_LOW,
- GPOEN_SYS_I2C2_DATA,
- GPI_SYS_I2C2_DATA)>;
- bias-disable; /* external pull-up */
- input-enable;
- input-schmitt-enable;
- };
- };
-
- i2c5_pins: i2c5-0 {
- i2c-pins {
- pinmux = <GPIOMUX(19, GPOUT_LOW,
- GPOEN_SYS_I2C5_CLK,
- GPI_SYS_I2C5_CLK)>,
- <GPIOMUX(20, GPOUT_LOW,
- GPOEN_SYS_I2C5_DATA,
- GPI_SYS_I2C5_DATA)>;
- bias-disable; /* external pull-up */
- input-enable;
- input-schmitt-enable;
- };
- };
-
- i2c6_pins: i2c6-0 {
- i2c-pins {
- pinmux = <GPIOMUX(16, GPOUT_LOW,
- GPOEN_SYS_I2C6_CLK,
- GPI_SYS_I2C6_CLK)>,
- <GPIOMUX(17, GPOUT_LOW,
- GPOEN_SYS_I2C6_DATA,
- GPI_SYS_I2C6_DATA)>;
- bias-disable; /* external pull-up */
- input-enable;
- input-schmitt-enable;
- };
- };
-
- mmc0_pins: mmc0-0 {
- rst-pins {
- pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
- GPOEN_ENABLE,
- GPI_NONE)>;
- bias-pull-up;
- drive-strength = <12>;
- input-disable;
- input-schmitt-disable;
- slew-rate = <0>;
- };
-
- mmc-pins {
- pinmux = <PINMUX(64, 0)>,
- <PINMUX(65, 0)>,
- <PINMUX(66, 0)>,
- <PINMUX(67, 0)>,
- <PINMUX(68, 0)>,
- <PINMUX(69, 0)>,
- <PINMUX(70, 0)>,
- <PINMUX(71, 0)>,
- <PINMUX(72, 0)>,
- <PINMUX(73, 0)>;
- bias-pull-up;
- drive-strength = <12>;
- input-enable;
- };
- };
-
- mmc1_pins: mmc1-0 {
- clk-pins {
- pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
- GPOEN_ENABLE,
- GPI_NONE)>;
- bias-pull-up;
- drive-strength = <12>;
- input-disable;
- input-schmitt-disable;
- slew-rate = <0>;
- };
-
- mmc-pins {
- pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
- GPOEN_SYS_SDIO1_CMD,
- GPI_SYS_SDIO1_CMD)>,
- <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
- GPOEN_SYS_SDIO1_DATA0,
- GPI_SYS_SDIO1_DATA0)>,
- <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
- GPOEN_SYS_SDIO1_DATA1,
- GPI_SYS_SDIO1_DATA1)>,
- <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
- GPOEN_SYS_SDIO1_DATA2,
- GPI_SYS_SDIO1_DATA2)>,
- <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
- GPOEN_SYS_SDIO1_DATA3,
- GPI_SYS_SDIO1_DATA3)>;
- bias-pull-up;
- drive-strength = <12>;
- input-enable;
- input-schmitt-enable;
- slew-rate = <0>;
- };
- };
-
- pwmdac_pins: pwmdac-0 {
- pwmdac-pins {
- pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
- GPOEN_ENABLE,
- GPI_NONE)>,
- <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
- GPOEN_ENABLE,
- GPI_NONE)>;
- bias-disable;
- drive-strength = <2>;
- input-disable;
- input-schmitt-disable;
- slew-rate = <0>;
- };
- };
-
- pwm_pins: pwm-0 {
- pwm-pins {
- pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
- GPOEN_SYS_PWM0_CHANNEL0,
- GPI_NONE)>,
- <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
- GPOEN_SYS_PWM0_CHANNEL1,
- GPI_NONE)>;
- bias-disable;
- drive-strength = <12>;
- input-disable;
- input-schmitt-disable;
- slew-rate = <0>;
- };
- };
-
- spi0_pins: spi0-0 {
- mosi-pins {
- pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
- GPOEN_ENABLE,
- GPI_NONE)>;
- bias-disable;
- input-disable;
- input-schmitt-disable;
- };
-
- miso-pins {
- pinmux = <GPIOMUX(53, GPOUT_LOW,
- GPOEN_DISABLE,
- GPI_SYS_SPI0_RXD)>;
- bias-pull-up;
- input-enable;
- input-schmitt-enable;
- };
-
- sck-pins {
- pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
- GPOEN_ENABLE,
- GPI_SYS_SPI0_CLK)>;
- bias-disable;
- input-disable;
- input-schmitt-disable;
- };
-
- ss-pins {
- pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
- GPOEN_ENABLE,
- GPI_SYS_SPI0_FSS)>;
- bias-disable;
- input-disable;
- input-schmitt-disable;
- };
- };
-
- uart0_pins: uart0-0 {
- tx-pins {
- pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
- GPOEN_ENABLE,
- GPI_NONE)>;
- bias-disable;
- drive-strength = <12>;
- input-disable;
- input-schmitt-disable;
- slew-rate = <0>;
- };
-
- rx-pins {
- pinmux = <GPIOMUX(6, GPOUT_LOW,
- GPOEN_DISABLE,
- GPI_SYS_UART0_RX)>;
- bias-disable; /* external pull-up */
- drive-strength = <2>;
- input-enable;
- input-schmitt-enable;
- slew-rate = <0>;
- };
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- status = "okay";
-};
-
-&usb0 {
- dr_mode = "peripheral";
- status = "okay";
-};
-
-&U74_1 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&U74_2 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&U74_3 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&U74_4 {
- cpu-supply = <&vdd_cpu>;
};
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 8/8] riscv: dts: starfive: add Milkv Mars board device tree
2024-04-29 0:13 [PATCH v4 0/8] riscv: dts: starfive: add Milkv Mars board device tree Jisheng Zhang
` (6 preceding siblings ...)
2024-04-29 0:13 ` [PATCH v4 7/8] riscv: dts: starfive: introduce a common board dtsi for jh7110 based boards Jisheng Zhang
@ 2024-04-29 0:13 ` Jisheng Zhang
2024-04-29 13:52 ` Emil Renner Berthing
2024-04-30 21:20 ` [PATCH v4 0/8] " Conor Dooley
8 siblings, 1 reply; 14+ messages in thread
From: Jisheng Zhang @ 2024-04-29 0:13 UTC (permalink / raw
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-kernel
The Milkv Mars is a development board based on the Starfive JH7110 SoC.
The board features:
- JH7110 SoC
- 1/2/4/8 GiB LPDDR4 DRAM
- AXP15060 PMIC
- 40 pin GPIO header
- 3x USB 3.0 host port
- 1x USB 2.0 host port
- 1x M.2 E-Key
- 1x eMMC slot
- 1x MicroSD slot
- 1x QSPI Flash
- 1x 1Gbps Ethernet port
- 1x HDMI port
- 1x 2-lane DSI and 1x 4-lane DSI
- 1x 2-lane CSI
Add the devicetree file describing the currently supported features,
namely PMIC, UART, I2C, GPIO, SD card, QSPI Flash, eMMC and Ethernet.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/boot/dts/starfive/Makefile | 1 +
.../boot/dts/starfive/jh7110-milkv-mars.dts | 30 +++++++++++++++++++
2 files changed, 31 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 0141504c0f5c..2fa0cd7f31c3 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -8,5 +8,6 @@ DTC_FLAGS_jh7110-starfive-visionfive-2-v1.3b := -@
dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
+dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
new file mode 100644
index 000000000000..fa0eac78e0ba
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/dts-v1/;
+#include "jh7110-common.dtsi"
+
+/ {
+ model = "Milk-V Mars";
+ compatible = "milkv,mars", "starfive,jh7110";
+};
+
+&gmac0 {
+ starfive,tx-use-rgmii-clk;
+ assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
+ assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
+};
+
+
+&phy0 {
+ motorcomm,tx-clk-adj-enabled;
+ motorcomm,tx-clk-10-inverted;
+ motorcomm,tx-clk-100-inverted;
+ motorcomm,tx-clk-1000-inverted;
+ motorcomm,rx-clk-drv-microamp = <3970>;
+ motorcomm,rx-data-drv-microamp = <2910>;
+ rx-internal-delay-ps = <1500>;
+ tx-internal-delay-ps = <1500>;
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v4 5/8] riscv: dts: starfive: visionfive 2: add tf cd-gpios
2024-04-29 0:13 ` [PATCH v4 5/8] riscv: dts: starfive: visionfive 2: add tf cd-gpios Jisheng Zhang
@ 2024-04-29 13:46 ` Emil Renner Berthing
0 siblings, 0 replies; 14+ messages in thread
From: Emil Renner Berthing @ 2024-04-29 13:46 UTC (permalink / raw
To: Jisheng Zhang, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-kernel
Jisheng Zhang wrote:
> Per VisionFive 2 1.2B, and 1.3A boards' SCH, GPIO 41 is used as
> card detect. So add "cd-gpios" property for this.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index 910c07bd4af9..b6030d63459d 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -303,7 +303,7 @@ &mmc1 {
> bus-width = <4>;
> no-sdio;
> no-mmc;
> - broken-cd;
> + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
nit if you need to respin this anyway: i know the properties are already not
sorted, but i'd prefer to not add more properties out of order.
In any case
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> cap-sd-highspeed;
> post-power-on-delay-ms = <200>;
> pinctrl-names = "default";
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 6/8] riscv: dts: starfive: visionfive 2: add "disable-wp" for tfcard
2024-04-29 0:13 ` [PATCH v4 6/8] riscv: dts: starfive: visionfive 2: add "disable-wp" for tfcard Jisheng Zhang
@ 2024-04-29 13:47 ` Emil Renner Berthing
0 siblings, 0 replies; 14+ messages in thread
From: Emil Renner Berthing @ 2024-04-29 13:47 UTC (permalink / raw
To: Jisheng Zhang, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-kernel
Jisheng Zhang wrote:
> No physical write-protect line is present, so setting "disable-wp".
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index b6030d63459d..e19f26628054 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -304,6 +304,7 @@ &mmc1 {
> no-sdio;
> no-mmc;
> cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> + disable-wp;
Same nit as patch 5/6, but in any case:
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> cap-sd-highspeed;
> post-power-on-delay-ms = <200>;
> pinctrl-names = "default";
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 7/8] riscv: dts: starfive: introduce a common board dtsi for jh7110 based boards
2024-04-29 0:13 ` [PATCH v4 7/8] riscv: dts: starfive: introduce a common board dtsi for jh7110 based boards Jisheng Zhang
@ 2024-04-29 13:51 ` Emil Renner Berthing
0 siblings, 0 replies; 14+ messages in thread
From: Emil Renner Berthing @ 2024-04-29 13:51 UTC (permalink / raw
To: Jisheng Zhang, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-kernel
Jisheng Zhang wrote:
> This is to prepare for Milkv Mars board dts support in the following
> patch. Let's factored out common part into .dtsi.
Maybe something like:
"Many boards using the StarFive JH7110 SoC share a lot of their design with the
first VisionFive 2 boards. Let's factor out the common parts in preparation for
adding support for the Milk-V Mars board."
In any case:
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> .../boot/dts/starfive/jh7110-common.dtsi | 599 ++++++++++++++++++
> .../jh7110-starfive-visionfive-2.dtsi | 585 +----------------
> 2 files changed, 600 insertions(+), 584 deletions(-)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-common.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> new file mode 100644
> index 000000000000..8ff6ea64f048
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> @@ -0,0 +1,599 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include "jh7110.dtsi"
> +#include "jh7110-pinfunc.h"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + aliases {
> + ethernet0 = &gmac0;
> + i2c0 = &i2c0;
> + i2c2 = &i2c2;
> + i2c5 = &i2c5;
> + i2c6 = &i2c6;
> + mmc0 = &mmc0;
> + mmc1 = &mmc1;
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0x1 0x0>;
> + };
> +
> + gpio-restart {
> + compatible = "gpio-restart";
> + gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
> + priority = <224>;
> + };
> +
> + pwmdac_codec: audio-codec {
> + compatible = "linux,spdif-dit";
> + #sound-dai-cells = <0>;
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + simple-audio-card,dai-link@0 {
> + reg = <0>;
> + format = "left_j";
> + bitclock-master = <&sndcpu0>;
> + frame-master = <&sndcpu0>;
> +
> + sndcpu0: cpu {
> + sound-dai = <&pwmdac>;
> + };
> +
> + codec {
> + sound-dai = <&pwmdac_codec>;
> + };
> + };
> + };
> +};
> +
> +&cpus {
> + timebase-frequency = <4000000>;
> +};
> +
> +&dvp_clk {
> + clock-frequency = <74250000>;
> +};
> +
> +&gmac0_rgmii_rxin {
> + clock-frequency = <125000000>;
> +};
> +
> +&gmac0_rmii_refin {
> + clock-frequency = <50000000>;
> +};
> +
> +&gmac1_rgmii_rxin {
> + clock-frequency = <125000000>;
> +};
> +
> +&gmac1_rmii_refin {
> + clock-frequency = <50000000>;
> +};
> +
> +&hdmitx0_pixelclk {
> + clock-frequency = <297000000>;
> +};
> +
> +&i2srx_bclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&i2srx_lrck_ext {
> + clock-frequency = <192000>;
> +};
> +
> +&i2stx_bclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&i2stx_lrck_ext {
> + clock-frequency = <192000>;
> +};
> +
> +&mclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&osc {
> + clock-frequency = <24000000>;
> +};
> +
> +&rtc_osc {
> + clock-frequency = <32768>;
> +};
> +
> +&tdm_ext {
> + clock-frequency = <49152000>;
> +};
> +
> +&camss {
> + assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
> + <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
> + assigned-clock-rates = <49500000>, <198000000>;
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + camss_from_csi2rx: endpoint {
> + remote-endpoint = <&csi2rx_to_camss>;
> + };
> + };
> + };
> +};
> +
> +&csi2rx {
> + assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
> + assigned-clock-rates = <297000000>;
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + /* remote MIPI sensor endpoint */
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + csi2rx_to_camss: endpoint {
> + remote-endpoint = <&camss_from_csi2rx>;
> + };
> + };
> + };
> +};
> +
> +&gmac0 {
> + phy-handle = <&phy0>;
> + phy-mode = "rgmii-id";
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
> +
> + phy0: ethernet-phy@0 {
> + reg = <0>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + clock-frequency = <100000>;
> + i2c-sda-hold-time-ns = <300>;
> + i2c-sda-falling-time-ns = <510>;
> + i2c-scl-falling-time-ns = <510>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + clock-frequency = <100000>;
> + i2c-sda-hold-time-ns = <300>;
> + i2c-sda-falling-time-ns = <510>;
> + i2c-scl-falling-time-ns = <510>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_pins>;
> + status = "okay";
> +};
> +
> +&i2c5 {
> + clock-frequency = <100000>;
> + i2c-sda-hold-time-ns = <300>;
> + i2c-sda-falling-time-ns = <510>;
> + i2c-scl-falling-time-ns = <510>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c5_pins>;
> + status = "okay";
> +
> + axp15060: pmic@36 {
> + compatible = "x-powers,axp15060";
> + reg = <0x36>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + regulators {
> + vcc_3v3: dcdc1 {
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc_3v3";
> + };
> +
> + vdd_cpu: dcdc2 {
> + regulator-always-on;
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1540000>;
> + regulator-name = "vdd-cpu";
> + };
> +
> + emmc_vdd: aldo4 {
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-name = "emmc_vdd";
> + };
> + };
> + };
> +};
> +
> +&i2c6 {
> + clock-frequency = <100000>;
> + i2c-sda-hold-time-ns = <300>;
> + i2c-sda-falling-time-ns = <510>;
> + i2c-scl-falling-time-ns = <510>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c6_pins>;
> + status = "okay";
> +};
> +
> +&mmc0 {
> + max-frequency = <100000000>;
> + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> + assigned-clock-rates = <50000000>;
> + bus-width = <8>;
> + cap-mmc-highspeed;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + cap-mmc-hw-reset;
> + post-power-on-delay-ms = <200>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins>;
> + vmmc-supply = <&vcc_3v3>;
> + vqmmc-supply = <&emmc_vdd>;
> + status = "okay";
> +};
> +
> +&mmc1 {
> + max-frequency = <100000000>;
> + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> + assigned-clock-rates = <50000000>;
> + bus-width = <4>;
> + no-sdio;
> + no-mmc;
> + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> + disable-wp;
> + cap-sd-highspeed;
> + post-power-on-delay-ms = <200>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc1_pins>;
> + status = "okay";
> +};
> +
> +&pwmdac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwmdac_pins>;
> + status = "okay";
> +};
> +
> +&qspi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + nor_flash: flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + cdns,read-delay = <5>;
> + spi-max-frequency = <12000000>;
> + cdns,tshsl-ns = <1>;
> + cdns,tsd2d-ns = <1>;
> + cdns,tchsh-ns = <1>;
> + cdns,tslch-ns = <1>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + spl@0 {
> + reg = <0x0 0x80000>;
> + };
> + uboot-env@f0000 {
> + reg = <0xf0000 0x10000>;
> + };
> + uboot@100000 {
> + reg = <0x100000 0x400000>;
> + };
> + reserved-data@600000 {
> + reg = <0x600000 0xa00000>;
> + };
> + };
> + };
> +};
> +
> +&pwm {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm_pins>;
> + status = "okay";
> +};
> +
> +&spi0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0_pins>;
> + status = "okay";
> +
> + spi_dev0: spi@0 {
> + compatible = "rohm,dh2228fv";
> + reg = <0>;
> + spi-max-frequency = <10000000>;
> + };
> +};
> +
> +&sysgpio {
> + i2c0_pins: i2c0-0 {
> + i2c-pins {
> + pinmux = <GPIOMUX(57, GPOUT_LOW,
> + GPOEN_SYS_I2C0_CLK,
> + GPI_SYS_I2C0_CLK)>,
> + <GPIOMUX(58, GPOUT_LOW,
> + GPOEN_SYS_I2C0_DATA,
> + GPI_SYS_I2C0_DATA)>;
> + bias-disable; /* external pull-up */
> + input-enable;
> + input-schmitt-enable;
> + };
> + };
> +
> + i2c2_pins: i2c2-0 {
> + i2c-pins {
> + pinmux = <GPIOMUX(3, GPOUT_LOW,
> + GPOEN_SYS_I2C2_CLK,
> + GPI_SYS_I2C2_CLK)>,
> + <GPIOMUX(2, GPOUT_LOW,
> + GPOEN_SYS_I2C2_DATA,
> + GPI_SYS_I2C2_DATA)>;
> + bias-disable; /* external pull-up */
> + input-enable;
> + input-schmitt-enable;
> + };
> + };
> +
> + i2c5_pins: i2c5-0 {
> + i2c-pins {
> + pinmux = <GPIOMUX(19, GPOUT_LOW,
> + GPOEN_SYS_I2C5_CLK,
> + GPI_SYS_I2C5_CLK)>,
> + <GPIOMUX(20, GPOUT_LOW,
> + GPOEN_SYS_I2C5_DATA,
> + GPI_SYS_I2C5_DATA)>;
> + bias-disable; /* external pull-up */
> + input-enable;
> + input-schmitt-enable;
> + };
> + };
> +
> + i2c6_pins: i2c6-0 {
> + i2c-pins {
> + pinmux = <GPIOMUX(16, GPOUT_LOW,
> + GPOEN_SYS_I2C6_CLK,
> + GPI_SYS_I2C6_CLK)>,
> + <GPIOMUX(17, GPOUT_LOW,
> + GPOEN_SYS_I2C6_DATA,
> + GPI_SYS_I2C6_DATA)>;
> + bias-disable; /* external pull-up */
> + input-enable;
> + input-schmitt-enable;
> + };
> + };
> +
> + mmc0_pins: mmc0-0 {
> + rst-pins {
> + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> + GPOEN_ENABLE,
> + GPI_NONE)>;
> + bias-pull-up;
> + drive-strength = <12>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + mmc-pins {
> + pinmux = <PINMUX(64, 0)>,
> + <PINMUX(65, 0)>,
> + <PINMUX(66, 0)>,
> + <PINMUX(67, 0)>,
> + <PINMUX(68, 0)>,
> + <PINMUX(69, 0)>,
> + <PINMUX(70, 0)>,
> + <PINMUX(71, 0)>,
> + <PINMUX(72, 0)>,
> + <PINMUX(73, 0)>;
> + bias-pull-up;
> + drive-strength = <12>;
> + input-enable;
> + };
> + };
> +
> + mmc1_pins: mmc1-0 {
> + clk-pins {
> + pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
> + GPOEN_ENABLE,
> + GPI_NONE)>;
> + bias-pull-up;
> + drive-strength = <12>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + mmc-pins {
> + pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
> + GPOEN_SYS_SDIO1_CMD,
> + GPI_SYS_SDIO1_CMD)>,
> + <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
> + GPOEN_SYS_SDIO1_DATA0,
> + GPI_SYS_SDIO1_DATA0)>,
> + <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
> + GPOEN_SYS_SDIO1_DATA1,
> + GPI_SYS_SDIO1_DATA1)>,
> + <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
> + GPOEN_SYS_SDIO1_DATA2,
> + GPI_SYS_SDIO1_DATA2)>,
> + <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
> + GPOEN_SYS_SDIO1_DATA3,
> + GPI_SYS_SDIO1_DATA3)>;
> + bias-pull-up;
> + drive-strength = <12>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> + };
> +
> + pwmdac_pins: pwmdac-0 {
> + pwmdac-pins {
> + pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
> + GPOEN_ENABLE,
> + GPI_NONE)>,
> + <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
> + GPOEN_ENABLE,
> + GPI_NONE)>;
> + bias-disable;
> + drive-strength = <2>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
> +
> + pwm_pins: pwm-0 {
> + pwm-pins {
> + pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
> + GPOEN_SYS_PWM0_CHANNEL0,
> + GPI_NONE)>,
> + <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
> + GPOEN_SYS_PWM0_CHANNEL1,
> + GPI_NONE)>;
> + bias-disable;
> + drive-strength = <12>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
> +
> + spi0_pins: spi0-0 {
> + mosi-pins {
> + pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
> + GPOEN_ENABLE,
> + GPI_NONE)>;
> + bias-disable;
> + input-disable;
> + input-schmitt-disable;
> + };
> +
> + miso-pins {
> + pinmux = <GPIOMUX(53, GPOUT_LOW,
> + GPOEN_DISABLE,
> + GPI_SYS_SPI0_RXD)>;
> + bias-pull-up;
> + input-enable;
> + input-schmitt-enable;
> + };
> +
> + sck-pins {
> + pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
> + GPOEN_ENABLE,
> + GPI_SYS_SPI0_CLK)>;
> + bias-disable;
> + input-disable;
> + input-schmitt-disable;
> + };
> +
> + ss-pins {
> + pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
> + GPOEN_ENABLE,
> + GPI_SYS_SPI0_FSS)>;
> + bias-disable;
> + input-disable;
> + input-schmitt-disable;
> + };
> + };
> +
> + uart0_pins: uart0-0 {
> + tx-pins {
> + pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
> + GPOEN_ENABLE,
> + GPI_NONE)>;
> + bias-disable;
> + drive-strength = <12>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + rx-pins {
> + pinmux = <GPIOMUX(6, GPOUT_LOW,
> + GPOEN_DISABLE,
> + GPI_SYS_UART0_RX)>;
> + bias-disable; /* external pull-up */
> + drive-strength = <2>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> + status = "okay";
> +};
> +
> +&usb0 {
> + dr_mode = "peripheral";
> + status = "okay";
> +};
> +
> +&U74_1 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_2 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_3 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_4 {
> + cpu-supply = <&vdd_cpu>;
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index e19f26628054..9d70f21c86fc 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -5,188 +5,11 @@
> */
>
> /dts-v1/;
> -#include "jh7110.dtsi"
> -#include "jh7110-pinfunc.h"
> -#include <dt-bindings/gpio/gpio.h>
> +#include "jh7110-common.dtsi"
>
> / {
> aliases {
> - ethernet0 = &gmac0;
> ethernet1 = &gmac1;
> - i2c0 = &i2c0;
> - i2c2 = &i2c2;
> - i2c5 = &i2c5;
> - i2c6 = &i2c6;
> - mmc0 = &mmc0;
> - mmc1 = &mmc1;
> - serial0 = &uart0;
> - };
> -
> - chosen {
> - stdout-path = "serial0:115200n8";
> - };
> -
> - memory@40000000 {
> - device_type = "memory";
> - reg = <0x0 0x40000000 0x1 0x0>;
> - };
> -
> - gpio-restart {
> - compatible = "gpio-restart";
> - gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
> - priority = <224>;
> - };
> -
> - pwmdac_codec: audio-codec {
> - compatible = "linux,spdif-dit";
> - #sound-dai-cells = <0>;
> - };
> -
> - sound {
> - compatible = "simple-audio-card";
> - simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - simple-audio-card,dai-link@0 {
> - reg = <0>;
> - format = "left_j";
> - bitclock-master = <&sndcpu0>;
> - frame-master = <&sndcpu0>;
> -
> - sndcpu0: cpu {
> - sound-dai = <&pwmdac>;
> - };
> -
> - codec {
> - sound-dai = <&pwmdac_codec>;
> - };
> - };
> - };
> -};
> -
> -&cpus {
> - timebase-frequency = <4000000>;
> -};
> -
> -&dvp_clk {
> - clock-frequency = <74250000>;
> -};
> -
> -&gmac0_rgmii_rxin {
> - clock-frequency = <125000000>;
> -};
> -
> -&gmac0_rmii_refin {
> - clock-frequency = <50000000>;
> -};
> -
> -&gmac1_rgmii_rxin {
> - clock-frequency = <125000000>;
> -};
> -
> -&gmac1_rmii_refin {
> - clock-frequency = <50000000>;
> -};
> -
> -&hdmitx0_pixelclk {
> - clock-frequency = <297000000>;
> -};
> -
> -&i2srx_bclk_ext {
> - clock-frequency = <12288000>;
> -};
> -
> -&i2srx_lrck_ext {
> - clock-frequency = <192000>;
> -};
> -
> -&i2stx_bclk_ext {
> - clock-frequency = <12288000>;
> -};
> -
> -&i2stx_lrck_ext {
> - clock-frequency = <192000>;
> -};
> -
> -&mclk_ext {
> - clock-frequency = <12288000>;
> -};
> -
> -&osc {
> - clock-frequency = <24000000>;
> -};
> -
> -&rtc_osc {
> - clock-frequency = <32768>;
> -};
> -
> -&tdm_ext {
> - clock-frequency = <49152000>;
> -};
> -
> -&camss {
> - assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
> - <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
> - assigned-clock-rates = <49500000>, <198000000>;
> - status = "okay";
> -
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port@0 {
> - reg = <0>;
> - };
> -
> - port@1 {
> - reg = <1>;
> -
> - camss_from_csi2rx: endpoint {
> - remote-endpoint = <&csi2rx_to_camss>;
> - };
> - };
> - };
> -};
> -
> -&csi2rx {
> - assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
> - assigned-clock-rates = <297000000>;
> - status = "okay";
> -
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port@0 {
> - reg = <0>;
> -
> - /* remote MIPI sensor endpoint */
> - };
> -
> - port@1 {
> - reg = <1>;
> -
> - csi2rx_to_camss: endpoint {
> - remote-endpoint = <&camss_from_csi2rx>;
> - };
> - };
> - };
> -};
> -
> -&gmac0 {
> - phy-handle = <&phy0>;
> - phy-mode = "rgmii-id";
> - status = "okay";
> -
> - mdio {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "snps,dwmac-mdio";
> -
> - phy0: ethernet-phy@0 {
> - reg = <0>;
> - };
> };
> };
>
> @@ -206,412 +29,6 @@ phy1: ethernet-phy@1 {
> };
> };
>
> -&i2c0 {
> - clock-frequency = <100000>;
> - i2c-sda-hold-time-ns = <300>;
> - i2c-sda-falling-time-ns = <510>;
> - i2c-scl-falling-time-ns = <510>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&i2c0_pins>;
> - status = "okay";
> -};
> -
> -&i2c2 {
> - clock-frequency = <100000>;
> - i2c-sda-hold-time-ns = <300>;
> - i2c-sda-falling-time-ns = <510>;
> - i2c-scl-falling-time-ns = <510>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&i2c2_pins>;
> - status = "okay";
> -};
> -
> -&i2c5 {
> - clock-frequency = <100000>;
> - i2c-sda-hold-time-ns = <300>;
> - i2c-sda-falling-time-ns = <510>;
> - i2c-scl-falling-time-ns = <510>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&i2c5_pins>;
> - status = "okay";
> -
> - axp15060: pmic@36 {
> - compatible = "x-powers,axp15060";
> - reg = <0x36>;
> - interrupt-controller;
> - #interrupt-cells = <1>;
> -
> - regulators {
> - vcc_3v3: dcdc1 {
> - regulator-boot-on;
> - regulator-always-on;
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-name = "vcc_3v3";
> - };
> -
> - vdd_cpu: dcdc2 {
> - regulator-always-on;
> - regulator-min-microvolt = <500000>;
> - regulator-max-microvolt = <1540000>;
> - regulator-name = "vdd-cpu";
> - };
> -
> - emmc_vdd: aldo4 {
> - regulator-boot-on;
> - regulator-always-on;
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-name = "emmc_vdd";
> - };
> - };
> - };
> -};
> -
> -&i2c6 {
> - clock-frequency = <100000>;
> - i2c-sda-hold-time-ns = <300>;
> - i2c-sda-falling-time-ns = <510>;
> - i2c-scl-falling-time-ns = <510>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&i2c6_pins>;
> - status = "okay";
> -};
> -
> &mmc0 {
> - max-frequency = <100000000>;
> - assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> - assigned-clock-rates = <50000000>;
> - bus-width = <8>;
> - cap-mmc-highspeed;
> - mmc-ddr-1_8v;
> - mmc-hs200-1_8v;
> non-removable;
> - cap-mmc-hw-reset;
> - post-power-on-delay-ms = <200>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins>;
> - vmmc-supply = <&vcc_3v3>;
> - vqmmc-supply = <&emmc_vdd>;
> - status = "okay";
> -};
> -
> -&mmc1 {
> - max-frequency = <100000000>;
> - assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> - assigned-clock-rates = <50000000>;
> - bus-width = <4>;
> - no-sdio;
> - no-mmc;
> - cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> - disable-wp;
> - cap-sd-highspeed;
> - post-power-on-delay-ms = <200>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&mmc1_pins>;
> - status = "okay";
> -};
> -
> -&pwmdac {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pwmdac_pins>;
> - status = "okay";
> -};
> -
> -&qspi {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "okay";
> -
> - nor_flash: flash@0 {
> - compatible = "jedec,spi-nor";
> - reg = <0>;
> - cdns,read-delay = <5>;
> - spi-max-frequency = <12000000>;
> - cdns,tshsl-ns = <1>;
> - cdns,tsd2d-ns = <1>;
> - cdns,tchsh-ns = <1>;
> - cdns,tslch-ns = <1>;
> -
> - partitions {
> - compatible = "fixed-partitions";
> - #address-cells = <1>;
> - #size-cells = <1>;
> -
> - spl@0 {
> - reg = <0x0 0x80000>;
> - };
> - uboot-env@f0000 {
> - reg = <0xf0000 0x10000>;
> - };
> - uboot@100000 {
> - reg = <0x100000 0x400000>;
> - };
> - reserved-data@600000 {
> - reg = <0x600000 0xa00000>;
> - };
> - };
> - };
> -};
> -
> -&pwm {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pwm_pins>;
> - status = "okay";
> -};
> -
> -&spi0 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&spi0_pins>;
> - status = "okay";
> -
> - spi_dev0: spi@0 {
> - compatible = "rohm,dh2228fv";
> - reg = <0>;
> - spi-max-frequency = <10000000>;
> - };
> -};
> -
> -&sysgpio {
> - i2c0_pins: i2c0-0 {
> - i2c-pins {
> - pinmux = <GPIOMUX(57, GPOUT_LOW,
> - GPOEN_SYS_I2C0_CLK,
> - GPI_SYS_I2C0_CLK)>,
> - <GPIOMUX(58, GPOUT_LOW,
> - GPOEN_SYS_I2C0_DATA,
> - GPI_SYS_I2C0_DATA)>;
> - bias-disable; /* external pull-up */
> - input-enable;
> - input-schmitt-enable;
> - };
> - };
> -
> - i2c2_pins: i2c2-0 {
> - i2c-pins {
> - pinmux = <GPIOMUX(3, GPOUT_LOW,
> - GPOEN_SYS_I2C2_CLK,
> - GPI_SYS_I2C2_CLK)>,
> - <GPIOMUX(2, GPOUT_LOW,
> - GPOEN_SYS_I2C2_DATA,
> - GPI_SYS_I2C2_DATA)>;
> - bias-disable; /* external pull-up */
> - input-enable;
> - input-schmitt-enable;
> - };
> - };
> -
> - i2c5_pins: i2c5-0 {
> - i2c-pins {
> - pinmux = <GPIOMUX(19, GPOUT_LOW,
> - GPOEN_SYS_I2C5_CLK,
> - GPI_SYS_I2C5_CLK)>,
> - <GPIOMUX(20, GPOUT_LOW,
> - GPOEN_SYS_I2C5_DATA,
> - GPI_SYS_I2C5_DATA)>;
> - bias-disable; /* external pull-up */
> - input-enable;
> - input-schmitt-enable;
> - };
> - };
> -
> - i2c6_pins: i2c6-0 {
> - i2c-pins {
> - pinmux = <GPIOMUX(16, GPOUT_LOW,
> - GPOEN_SYS_I2C6_CLK,
> - GPI_SYS_I2C6_CLK)>,
> - <GPIOMUX(17, GPOUT_LOW,
> - GPOEN_SYS_I2C6_DATA,
> - GPI_SYS_I2C6_DATA)>;
> - bias-disable; /* external pull-up */
> - input-enable;
> - input-schmitt-enable;
> - };
> - };
> -
> - mmc0_pins: mmc0-0 {
> - rst-pins {
> - pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> - GPOEN_ENABLE,
> - GPI_NONE)>;
> - bias-pull-up;
> - drive-strength = <12>;
> - input-disable;
> - input-schmitt-disable;
> - slew-rate = <0>;
> - };
> -
> - mmc-pins {
> - pinmux = <PINMUX(64, 0)>,
> - <PINMUX(65, 0)>,
> - <PINMUX(66, 0)>,
> - <PINMUX(67, 0)>,
> - <PINMUX(68, 0)>,
> - <PINMUX(69, 0)>,
> - <PINMUX(70, 0)>,
> - <PINMUX(71, 0)>,
> - <PINMUX(72, 0)>,
> - <PINMUX(73, 0)>;
> - bias-pull-up;
> - drive-strength = <12>;
> - input-enable;
> - };
> - };
> -
> - mmc1_pins: mmc1-0 {
> - clk-pins {
> - pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
> - GPOEN_ENABLE,
> - GPI_NONE)>;
> - bias-pull-up;
> - drive-strength = <12>;
> - input-disable;
> - input-schmitt-disable;
> - slew-rate = <0>;
> - };
> -
> - mmc-pins {
> - pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
> - GPOEN_SYS_SDIO1_CMD,
> - GPI_SYS_SDIO1_CMD)>,
> - <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
> - GPOEN_SYS_SDIO1_DATA0,
> - GPI_SYS_SDIO1_DATA0)>,
> - <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
> - GPOEN_SYS_SDIO1_DATA1,
> - GPI_SYS_SDIO1_DATA1)>,
> - <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
> - GPOEN_SYS_SDIO1_DATA2,
> - GPI_SYS_SDIO1_DATA2)>,
> - <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
> - GPOEN_SYS_SDIO1_DATA3,
> - GPI_SYS_SDIO1_DATA3)>;
> - bias-pull-up;
> - drive-strength = <12>;
> - input-enable;
> - input-schmitt-enable;
> - slew-rate = <0>;
> - };
> - };
> -
> - pwmdac_pins: pwmdac-0 {
> - pwmdac-pins {
> - pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
> - GPOEN_ENABLE,
> - GPI_NONE)>,
> - <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
> - GPOEN_ENABLE,
> - GPI_NONE)>;
> - bias-disable;
> - drive-strength = <2>;
> - input-disable;
> - input-schmitt-disable;
> - slew-rate = <0>;
> - };
> - };
> -
> - pwm_pins: pwm-0 {
> - pwm-pins {
> - pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
> - GPOEN_SYS_PWM0_CHANNEL0,
> - GPI_NONE)>,
> - <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
> - GPOEN_SYS_PWM0_CHANNEL1,
> - GPI_NONE)>;
> - bias-disable;
> - drive-strength = <12>;
> - input-disable;
> - input-schmitt-disable;
> - slew-rate = <0>;
> - };
> - };
> -
> - spi0_pins: spi0-0 {
> - mosi-pins {
> - pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
> - GPOEN_ENABLE,
> - GPI_NONE)>;
> - bias-disable;
> - input-disable;
> - input-schmitt-disable;
> - };
> -
> - miso-pins {
> - pinmux = <GPIOMUX(53, GPOUT_LOW,
> - GPOEN_DISABLE,
> - GPI_SYS_SPI0_RXD)>;
> - bias-pull-up;
> - input-enable;
> - input-schmitt-enable;
> - };
> -
> - sck-pins {
> - pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
> - GPOEN_ENABLE,
> - GPI_SYS_SPI0_CLK)>;
> - bias-disable;
> - input-disable;
> - input-schmitt-disable;
> - };
> -
> - ss-pins {
> - pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
> - GPOEN_ENABLE,
> - GPI_SYS_SPI0_FSS)>;
> - bias-disable;
> - input-disable;
> - input-schmitt-disable;
> - };
> - };
> -
> - uart0_pins: uart0-0 {
> - tx-pins {
> - pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
> - GPOEN_ENABLE,
> - GPI_NONE)>;
> - bias-disable;
> - drive-strength = <12>;
> - input-disable;
> - input-schmitt-disable;
> - slew-rate = <0>;
> - };
> -
> - rx-pins {
> - pinmux = <GPIOMUX(6, GPOUT_LOW,
> - GPOEN_DISABLE,
> - GPI_SYS_UART0_RX)>;
> - bias-disable; /* external pull-up */
> - drive-strength = <2>;
> - input-enable;
> - input-schmitt-enable;
> - slew-rate = <0>;
> - };
> - };
> -};
> -
> -&uart0 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&uart0_pins>;
> - status = "okay";
> -};
> -
> -&usb0 {
> - dr_mode = "peripheral";
> - status = "okay";
> -};
> -
> -&U74_1 {
> - cpu-supply = <&vdd_cpu>;
> -};
> -
> -&U74_2 {
> - cpu-supply = <&vdd_cpu>;
> -};
> -
> -&U74_3 {
> - cpu-supply = <&vdd_cpu>;
> -};
> -
> -&U74_4 {
> - cpu-supply = <&vdd_cpu>;
> };
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 8/8] riscv: dts: starfive: add Milkv Mars board device tree
2024-04-29 0:13 ` [PATCH v4 8/8] riscv: dts: starfive: add Milkv Mars board device tree Jisheng Zhang
@ 2024-04-29 13:52 ` Emil Renner Berthing
0 siblings, 0 replies; 14+ messages in thread
From: Emil Renner Berthing @ 2024-04-29 13:52 UTC (permalink / raw
To: Jisheng Zhang, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-kernel
Jisheng Zhang wrote:
> The Milkv Mars is a development board based on the Starfive JH7110 SoC.
> The board features:
>
> - JH7110 SoC
> - 1/2/4/8 GiB LPDDR4 DRAM
> - AXP15060 PMIC
> - 40 pin GPIO header
> - 3x USB 3.0 host port
> - 1x USB 2.0 host port
> - 1x M.2 E-Key
> - 1x eMMC slot
> - 1x MicroSD slot
> - 1x QSPI Flash
> - 1x 1Gbps Ethernet port
> - 1x HDMI port
> - 1x 2-lane DSI and 1x 4-lane DSI
> - 1x 2-lane CSI
>
> Add the devicetree file describing the currently supported features,
> namely PMIC, UART, I2C, GPIO, SD card, QSPI Flash, eMMC and Ethernet.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 0/8] riscv: dts: starfive: add Milkv Mars board device tree
2024-04-29 0:13 [PATCH v4 0/8] riscv: dts: starfive: add Milkv Mars board device tree Jisheng Zhang
` (7 preceding siblings ...)
2024-04-29 0:13 ` [PATCH v4 8/8] riscv: dts: starfive: add Milkv Mars board device tree Jisheng Zhang
@ 2024-04-30 21:20 ` Conor Dooley
8 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2024-04-30 21:20 UTC (permalink / raw
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing, Jisheng Zhang
Cc: Conor Dooley, linux-riscv, devicetree, linux-kernel
From: Conor Dooley <conor.dooley@microchip.com>
On Mon, 29 Apr 2024 08:13:09 +0800, Jisheng Zhang wrote:
> The Milkv Mars is a development board based on the Starfive JH7110 SoC.
> The board features:
>
> - JH7110 SoC
> - 1/2/4/8 GiB LPDDR4 DRAM
> - AXP15060 PMIC
> - 40 pin GPIO header
> - 3x USB 3.0 host port
> - 1x USB 2.0 host port
> - 1x M.2 E-Key
> - 1x eMMC slot
> - 1x MicroSD slot
> - 1x QSPI Flash
> - 1x 1Gbps Ethernet port
> - 1x HDMI port
> - 1x 2-lane DSI and 1x 4-lane DSI
> - 1x 2-lane CSI
>
> [...]
Applied to riscv-dt-for-next, thanks! I fixed up the nits of Emil's in
the merge commit.
[1/8] riscv: dts: starfive: add 'cpus' label to jh7110 and jh7100 soc dtsi
https://git.kernel.org/conor/c/5e7922abddd4
[2/8] dt-bindings: riscv: starfive: add Milkv Mars board
https://git.kernel.org/conor/c/4c536aa462f1
[3/8] riscv: dts: starfive: visionfive 2: update sound and codec dt node name
https://git.kernel.org/conor/c/b9a1481f259c
[4/8] riscv: dts: starfive: visionfive 2: use cpus label for timebase freq
https://git.kernel.org/conor/c/ffddddf4aa8d
[5/8] riscv: dts: starfive: visionfive 2: add tf cd-gpios
https://git.kernel.org/conor/c/0ffce9d49abd
[6/8] riscv: dts: starfive: visionfive 2: add "disable-wp" for tfcard
https://git.kernel.org/conor/c/07da6ddf510b
[7/8] riscv: dts: starfive: introduce a common board dtsi for jh7110 based boards
https://git.kernel.org/conor/c/ac9a37e2d6b6
[8/8] riscv: dts: starfive: add Milkv Mars board device tree
https://git.kernel.org/conor/c/9276badd9d03
Thanks,
Conor.
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2024-04-30 21:22 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-04-29 0:13 [PATCH v4 0/8] riscv: dts: starfive: add Milkv Mars board device tree Jisheng Zhang
2024-04-29 0:13 ` [PATCH v4 1/8] riscv: dts: starfive: add 'cpus' label to jh7110 and jh7100 soc dtsi Jisheng Zhang
2024-04-29 0:13 ` [PATCH v4 2/8] dt-bindings: riscv: starfive: add Milkv Mars board Jisheng Zhang
2024-04-29 0:13 ` [PATCH v4 3/8] riscv: dts: starfive: visionfive 2: update sound and codec dt node name Jisheng Zhang
2024-04-29 0:13 ` [PATCH v4 4/8] riscv: dts: starfive: visionfive 2: use cpus label for timebase freq Jisheng Zhang
2024-04-29 0:13 ` [PATCH v4 5/8] riscv: dts: starfive: visionfive 2: add tf cd-gpios Jisheng Zhang
2024-04-29 13:46 ` Emil Renner Berthing
2024-04-29 0:13 ` [PATCH v4 6/8] riscv: dts: starfive: visionfive 2: add "disable-wp" for tfcard Jisheng Zhang
2024-04-29 13:47 ` Emil Renner Berthing
2024-04-29 0:13 ` [PATCH v4 7/8] riscv: dts: starfive: introduce a common board dtsi for jh7110 based boards Jisheng Zhang
2024-04-29 13:51 ` Emil Renner Berthing
2024-04-29 0:13 ` [PATCH v4 8/8] riscv: dts: starfive: add Milkv Mars board device tree Jisheng Zhang
2024-04-29 13:52 ` Emil Renner Berthing
2024-04-30 21:20 ` [PATCH v4 0/8] " Conor Dooley
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