* [PATCH 0/2 v3] gpio: msm7200a: Add gpiolib support for MSM chips.
@ 2010-06-12 18:59 Gregory Bean
2010-06-12 18:59 ` [PATCH 1/2 " Gregory Bean
2010-06-12 18:59 ` [PATCH 2/2 v3] gpio: msm7200a: Add irq support to msm-gpiolib Gregory Bean
0 siblings, 2 replies; 3+ messages in thread
From: Gregory Bean @ 2010-06-12 18:59 UTC (permalink / raw
To: akpm; +Cc: linux-arm-msm, linux-kernel, Gregory Bean
Hi folks:
Here is a proposed driver which adds gpio and irq support to all
currently-supported arm-msm SoCs. Feedback is greatly appreciated.
Revision history:
v2: Cleaned up some housekeeping noise in probe and remove methods.
v3: Incorporated feedback from ben-linux@fluff.org.
Gregory Bean (2):
gpio: msm7200a: Add gpiolib support for MSM chips.
gpio: msm7200a: Add irq support to msm-gpiolib.
MAINTAINERS | 2 +
drivers/gpio/Kconfig | 8 +
drivers/gpio/Makefile | 1 +
drivers/gpio/msm7200a-gpio.c | 358 +++++++++++++++++++++++++++++++++++++++++
include/linux/msm7200a-gpio.h | 87 ++++++++++
5 files changed, 456 insertions(+), 0 deletions(-)
create mode 100644 drivers/gpio/msm7200a-gpio.c
create mode 100644 include/linux/msm7200a-gpio.h
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 1/2 v3] gpio: msm7200a: Add gpiolib support for MSM chips.
2010-06-12 18:59 [PATCH 0/2 v3] gpio: msm7200a: Add gpiolib support for MSM chips Gregory Bean
@ 2010-06-12 18:59 ` Gregory Bean
2010-06-12 18:59 ` [PATCH 2/2 v3] gpio: msm7200a: Add irq support to msm-gpiolib Gregory Bean
1 sibling, 0 replies; 3+ messages in thread
From: Gregory Bean @ 2010-06-12 18:59 UTC (permalink / raw
To: akpm
Cc: linux-arm-msm, linux-kernel, Gregory Bean, Joe Perches,
David S. Miller, Samuel Ortiz, Mark Brown, Randy Dunlap,
Michael Hennerich, Mike Frysinger, David Brown, Daniel Walker,
Bryan Huntsman
Add support for uniprocessor MSM chips whose TLMM/GPIO design
is the same as the MSM7200A.
This includes, but is not necessarily limited to, the:
MSM7200A, MSM7x25, MSM7x27, MSM7x30, QSD8x50, QSD8x50A
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
---
MAINTAINERS | 2 +
drivers/gpio/Kconfig | 8 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/msm7200a-gpio.c | 191 +++++++++++++++++++++++++++++++++++++++++
include/linux/msm7200a-gpio.h | 62 +++++++++++++
5 files changed, 264 insertions(+), 0 deletions(-)
create mode 100644 drivers/gpio/msm7200a-gpio.c
create mode 100644 include/linux/msm7200a-gpio.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 6d119c9..bdfd31d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -819,6 +819,8 @@ F: drivers/mmc/host/msm_sdcc.c
F: drivers/mmc/host/msm_sdcc.h
F: drivers/serial/msm_serial.h
F: drivers/serial/msm_serial.c
+F: drivers/gpio/msm7200a-gpio.c
+F: include/linux/msm7200a-gpio.h
T: git git://codeaurora.org/quic/kernel/dwalker/linux-msm.git
S: Maintained
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 724038d..557738a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -76,6 +76,14 @@ config GPIO_IT8761E
help
Say yes here to support GPIO functionality of IT8761E super I/O chip.
+config GPIO_MSM7200A
+ tristate "Qualcomm MSM7200A SoC GPIO support"
+ depends on GPIOLIB
+ help
+ Say yes here to support GPIO functionality on Qualcomm's
+ MSM chipsets which descend from the MSM7200a:
+ MSM7x01(a), MSM7x25, MSM7x27, MSM7x30, QSD8x50(a).
+
config GPIO_PL061
bool "PrimeCell PL061 GPIO support"
depends on ARM_AMBA
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 51c3cdd..2389c29 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_GPIO_MAX7301) += max7301.o
obj-$(CONFIG_GPIO_MAX732X) += max732x.o
obj-$(CONFIG_GPIO_MC33880) += mc33880.o
obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o
+obj-$(CONFIG_GPIO_MSM7200A) += msm7200a-gpio.o
obj-$(CONFIG_GPIO_PCA953X) += pca953x.o
obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o
obj-$(CONFIG_GPIO_PL061) += pl061.o
diff --git a/drivers/gpio/msm7200a-gpio.c b/drivers/gpio/msm7200a-gpio.c
new file mode 100644
index 0000000..21de253
--- /dev/null
+++ b/drivers/gpio/msm7200a-gpio.c
@@ -0,0 +1,191 @@
+/*
+ * Driver for Qualcomm MSM7200a and related SoC GPIO.
+ * Supported chipset families include:
+ * MSM7x01(a), MSM7x25, MSM7x27, MSM7x30, QSD8x50(a)
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/msm7200a-gpio.h>
+
+struct msm_gpio_dev {
+ struct gpio_chip gpio_chip;
+ spinlock_t lock;
+ struct msm7200a_gpio_regs regs;
+};
+
+static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip)
+{
+ return container_of(chip, struct msm_gpio_dev, gpio_chip);
+}
+
+static inline unsigned bit(unsigned offset)
+{
+ return 1U << offset;
+}
+
+/*
+ * This function assumes that msm_gpio_dev::lock is held.
+ */
+static inline void set_gpio_bit(unsigned n, void __iomem *reg)
+{
+ writel(readl(reg) | bit(n), reg);
+}
+
+/*
+ * This function assumes that msm_gpio_dev::lock is held.
+ */
+static inline void clr_gpio_bit(unsigned n, void __iomem *reg)
+{
+ writel(readl(reg) & ~bit(n), reg);
+}
+
+/*
+ * This function assumes that msm_gpio_dev::lock is held.
+ */
+static inline void
+msm_gpio_write(struct msm_gpio_dev *dev, unsigned n, unsigned on)
+{
+ if (on)
+ set_gpio_bit(n, dev->regs.out);
+ else
+ clr_gpio_bit(n, dev->regs.out);
+}
+
+static int gpio_chip_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+ struct msm_gpio_dev *msm_gpio = to_msm_gpio_dev(chip);
+ unsigned long irq_flags;
+
+ spin_lock_irqsave(&msm_gpio->lock, irq_flags);
+ clr_gpio_bit(offset, msm_gpio->regs.oe);
+ spin_unlock_irqrestore(&msm_gpio->lock, irq_flags);
+
+ return 0;
+}
+
+static int
+gpio_chip_direction_output(struct gpio_chip *chip, unsigned offset, int value)
+{
+ struct msm_gpio_dev *msm_gpio = to_msm_gpio_dev(chip);
+ unsigned long irq_flags;
+
+ spin_lock_irqsave(&msm_gpio->lock, irq_flags);
+ msm_gpio_write(msm_gpio, offset, value);
+ set_gpio_bit(offset, msm_gpio->regs.oe);
+ spin_unlock_irqrestore(&msm_gpio->lock, irq_flags);
+
+ return 0;
+}
+
+static int gpio_chip_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct msm_gpio_dev *msm_gpio = to_msm_gpio_dev(chip);
+
+ return readl(msm_gpio->regs.in) & bit(offset) ? 1 : 0;
+}
+
+static void gpio_chip_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ struct msm_gpio_dev *msm_gpio = to_msm_gpio_dev(chip);
+ unsigned long irq_flags;
+
+ spin_lock_irqsave(&msm_gpio->lock, irq_flags);
+ msm_gpio_write(msm_gpio, offset, value);
+ spin_unlock_irqrestore(&msm_gpio->lock, irq_flags);
+}
+
+static int msm_gpio_probe(struct platform_device *dev)
+{
+ struct msm_gpio_dev *msm_gpio;
+ struct msm7200a_gpio_platform_data *pdata = dev->dev.platform_data;
+ int ret;
+
+ if (!pdata)
+ return -EINVAL;
+
+ msm_gpio = kzalloc(sizeof(struct msm_gpio_dev), GFP_KERNEL);
+ if (!msm_gpio)
+ return -ENOMEM;
+
+ spin_lock_init(&msm_gpio->lock);
+ platform_set_drvdata(dev, msm_gpio);
+
+ msm_gpio->regs = pdata->regs;
+ msm_gpio->gpio_chip.label = dev->name;
+ msm_gpio->gpio_chip.base = pdata->gpio_base;
+ msm_gpio->gpio_chip.ngpio = pdata->ngpio;
+ msm_gpio->gpio_chip.direction_input = gpio_chip_direction_input;
+ msm_gpio->gpio_chip.direction_output = gpio_chip_direction_output;
+ msm_gpio->gpio_chip.get = gpio_chip_get;
+ msm_gpio->gpio_chip.set = gpio_chip_set;
+
+ ret = gpiochip_add(&msm_gpio->gpio_chip);
+ if (ret < 0)
+ goto err_post_malloc;
+
+ return ret;
+err_post_malloc:
+ kfree(msm_gpio);
+ return ret;
+}
+
+static int msm_gpio_remove(struct platform_device *dev)
+{
+ struct msm_gpio_dev *msm_gpio = platform_get_drvdata(dev);
+ int ret = gpiochip_remove(&msm_gpio->gpio_chip);
+
+ if (ret < 0)
+ return ret;
+
+ kfree(msm_gpio);
+
+ return 0;
+}
+
+static struct platform_driver msm_gpio_driver = {
+ .probe = msm_gpio_probe,
+ .remove = msm_gpio_remove,
+ .driver = {
+ .name = "msm7200a-gpio",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init msm_gpio_init(void)
+{
+ return platform_driver_register(&msm_gpio_driver);
+}
+
+static void __exit msm_gpio_exit(void)
+{
+ platform_driver_unregister(&msm_gpio_driver);
+}
+
+postcore_initcall(msm_gpio_init);
+module_exit(msm_gpio_exit);
+
+MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
+MODULE_DESCRIPTION("Driver for Qualcomm MSM 7200a-family SoC GPIOs");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:msm7200a-gpio");
diff --git a/include/linux/msm7200a-gpio.h b/include/linux/msm7200a-gpio.h
new file mode 100644
index 0000000..c44d16b
--- /dev/null
+++ b/include/linux/msm7200a-gpio.h
@@ -0,0 +1,62 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef __LINUX_MSM7200A_GPIO_H
+#define __LINUX_MSM7200A_GPIO_H
+
+/**
+ * struct msm7200a_gpio_regs - addresess of iomapped GPIO registers
+ * @in: GPIO_IN_n
+ * @out: GPIO_OUT_n
+ * @oe: GPIO_OE_n
+ *
+ * Registers are not guaranteed to be packed in memory, or even
+ * located in a predictable pattern.
+ */
+struct msm7200a_gpio_regs {
+ void __iomem *in;
+ void __iomem *out;
+ void __iomem *oe;
+};
+
+/**
+ * struct msm7200a_gpio_platform_data - configuration for msm7200a-gpio
+ * @gpio_base: The first gpio to be assigned to the device. Corresponds
+ * directly to gpio_chip.base.
+ * @ngpio: The number of gpio lines to be managed by the device.
+ * Must be <= 32. Corresponds directly to gpio_chip.ngpio.
+ * @regs: Addresses of the registers which control the gpios
+ * to be managed by the device.
+ */
+struct msm7200a_gpio_platform_data {
+ unsigned gpio_base;
+ unsigned ngpio;
+ struct msm7200a_gpio_regs regs;
+};
+
+#endif
--
1.7.0.4
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2 v3] gpio: msm7200a: Add irq support to msm-gpiolib.
2010-06-12 18:59 [PATCH 0/2 v3] gpio: msm7200a: Add gpiolib support for MSM chips Gregory Bean
2010-06-12 18:59 ` [PATCH 1/2 " Gregory Bean
@ 2010-06-12 18:59 ` Gregory Bean
1 sibling, 0 replies; 3+ messages in thread
From: Gregory Bean @ 2010-06-12 18:59 UTC (permalink / raw
To: akpm
Cc: linux-arm-msm, linux-kernel, Gregory Bean, David Brown,
Daniel Walker, Bryan Huntsman
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
---
drivers/gpio/msm7200a-gpio.c | 169 ++++++++++++++++++++++++++++++++++++++++-
include/linux/msm7200a-gpio.h | 25 ++++++
2 files changed, 193 insertions(+), 1 deletions(-)
diff --git a/drivers/gpio/msm7200a-gpio.c b/drivers/gpio/msm7200a-gpio.c
index 21de253..0e0d38d 100644
--- a/drivers/gpio/msm7200a-gpio.c
+++ b/drivers/gpio/msm7200a-gpio.c
@@ -23,6 +23,8 @@
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
@@ -31,6 +33,9 @@
struct msm_gpio_dev {
struct gpio_chip gpio_chip;
spinlock_t lock;
+ unsigned irq_base;
+ unsigned irq_summary;
+ bool latch_level_irqs;
struct msm7200a_gpio_regs regs;
};
@@ -115,11 +120,131 @@ static void gpio_chip_set(struct gpio_chip *chip, unsigned offset, int value)
spin_unlock_irqrestore(&msm_gpio->lock, irq_flags);
}
+static int gpio_chip_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct msm_gpio_dev *msm_gpio = to_msm_gpio_dev(chip);
+ return msm_gpio->irq_base + offset;
+}
+
+static void forget_level_irq(struct msm_gpio_dev *msm_gpio, unsigned offset)
+{
+ if (!msm_gpio->latch_level_irqs) {
+ unsigned v = readl(msm_gpio->regs.int_edge);
+ unsigned b = bit(offset);
+
+ if (!(v & b))
+ writel(b, msm_gpio->regs.int_clear);
+ }
+}
+
+static void msm_gpio_irq_mask(unsigned int irq)
+{
+ unsigned long irq_flags;
+ struct msm_gpio_dev *msm_gpio = get_irq_chip_data(irq);
+ unsigned offset = irq - msm_gpio->irq_base;
+
+ spin_lock_irqsave(&msm_gpio->lock, irq_flags);
+ forget_level_irq(msm_gpio, offset);
+ clr_gpio_bit(offset, msm_gpio->regs.int_en);
+ spin_unlock_irqrestore(&msm_gpio->lock, irq_flags);
+}
+
+static void msm_gpio_irq_unmask(unsigned int irq)
+{
+ unsigned long irq_flags;
+ struct msm_gpio_dev *msm_gpio = get_irq_chip_data(irq);
+ unsigned offset = irq - msm_gpio->irq_base;
+
+ spin_lock_irqsave(&msm_gpio->lock, irq_flags);
+ forget_level_irq(msm_gpio, offset);
+ set_gpio_bit(offset, msm_gpio->regs.int_en);
+ spin_unlock_irqrestore(&msm_gpio->lock, irq_flags);
+}
+
+static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+ unsigned long irq_flags;
+ struct msm_gpio_dev *msm_gpio = get_irq_chip_data(irq);
+ unsigned offset = irq - msm_gpio->irq_base;
+
+ if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
+ return -ENOTSUPP;
+
+ if ((flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) ==
+ (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW))
+ return -ENOTSUPP;
+
+ spin_lock_irqsave(&msm_gpio->lock, irq_flags);
+
+ if (flow_type & IRQ_TYPE_EDGE_BOTH) {
+ set_gpio_bit(offset, msm_gpio->regs.int_edge);
+ irq_desc[irq].handle_irq = handle_edge_irq;
+ } else {
+ clr_gpio_bit(offset, msm_gpio->regs.int_edge);
+ irq_desc[irq].handle_irq = handle_level_irq;
+ }
+
+ if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_RISING))
+ set_gpio_bit(offset, msm_gpio->regs.int_pos);
+ else
+ clr_gpio_bit(offset, msm_gpio->regs.int_pos);
+
+ spin_unlock_irqrestore(&msm_gpio->lock, irq_flags);
+
+ return 0;
+}
+
+static void msm_gpio_irq_mask_ack(unsigned int irq)
+{
+ msm_gpio_irq_mask(irq);
+}
+
+static irqreturn_t msm_gpio_irq_handler(int irq, void *dev)
+{
+ struct msm_gpio_dev *msm_gpio = dev;
+ unsigned long irq_flags;
+ unsigned e, s, triggered_irqs;
+ int b;
+
+ /*
+ * The int_status register latches trigger events whether or not
+ * the gpio line is enabled as an interrupt source. Therefore,
+ * the set of pins which defines the interrupts which need to fire
+ * is the intersection of int_status and int_en - int_status
+ * alone provides an incomplete picture.
+ */
+ spin_lock_irqsave(&msm_gpio->lock, irq_flags);
+ s = readl(msm_gpio->regs.int_status);
+ e = readl(msm_gpio->regs.int_en);
+ triggered_irqs = s & e;
+ if (triggered_irqs)
+ writel(triggered_irqs, msm_gpio->regs.int_clear);
+ spin_unlock_irqrestore(&msm_gpio->lock, irq_flags);
+
+ if (!triggered_irqs)
+ return IRQ_NONE;
+
+ while (triggered_irqs) {
+ b = ffs(triggered_irqs) - 1;
+ triggered_irqs &= ~bit(b);
+ generic_handle_irq(msm_gpio->irq_base + b);
+ }
+ return IRQ_HANDLED;
+}
+
+static struct irq_chip msm_gpio_irq_chip = {
+ .name = "msm_gpio",
+ .mask = msm_gpio_irq_mask,
+ .mask_ack = msm_gpio_irq_mask_ack,
+ .unmask = msm_gpio_irq_unmask,
+ .set_type = msm_gpio_irq_set_type,
+};
+
static int msm_gpio_probe(struct platform_device *dev)
{
struct msm_gpio_dev *msm_gpio;
struct msm7200a_gpio_platform_data *pdata = dev->dev.platform_data;
- int ret;
+ int i, irq, ret;
if (!pdata)
return -EINVAL;
@@ -139,12 +264,53 @@ static int msm_gpio_probe(struct platform_device *dev)
msm_gpio->gpio_chip.direction_output = gpio_chip_direction_output;
msm_gpio->gpio_chip.get = gpio_chip_get;
msm_gpio->gpio_chip.set = gpio_chip_set;
+ msm_gpio->gpio_chip.to_irq = gpio_chip_to_irq;
+ msm_gpio->irq_base = pdata->irq_base;
+ msm_gpio->irq_summary = pdata->irq_summary;
+ msm_gpio->latch_level_irqs = pdata->latch_level_irqs;
ret = gpiochip_add(&msm_gpio->gpio_chip);
if (ret < 0)
goto err_post_malloc;
+ for (i = 0; i < msm_gpio->gpio_chip.ngpio; ++i) {
+ irq = msm_gpio->irq_base + i;
+ set_irq_chip_data(irq, msm_gpio);
+ set_irq_chip(irq, &msm_gpio_irq_chip);
+ set_irq_handler(irq, handle_level_irq);
+ set_irq_flags(irq, IRQF_VALID);
+ }
+
+ /*
+ * We use a level-triggered interrupt because of the nature
+ * of the shared GPIO-group interrupt.
+ *
+ * Many GPIO chips may be sharing the same group IRQ line, and
+ * it is possible for GPIO interrupt to re-occur while the system
+ * is still servicing the group interrupt associated with it.
+ * The group IRQ line would not de-assert and re-assert, and
+ * we'd get no second edge to cause the group IRQ to be handled again.
+ *
+ * Using a level interrupt guarantees that the group IRQ handlers
+ * will continue to be called as long as any GPIO chip in the group
+ * is asserting, even if the condition began while the group
+ * handler was in mid-pass.
+ */
+ ret = request_irq(msm_gpio->irq_summary,
+ msm_gpio_irq_handler,
+ IRQF_SHARED | IRQF_TRIGGER_HIGH,
+ dev_name(&dev->dev),
+ msm_gpio);
+ if (ret < 0)
+ goto err_post_gpiochip_add;
+
return ret;
+err_post_gpiochip_add:
+ /*
+ * Under no circumstances should a line be held on a gpiochip
+ * which hasn't finished probing.
+ */
+ BUG_ON(gpiochip_remove(&msm_gpio->gpio_chip) < 0);
err_post_malloc:
kfree(msm_gpio);
return ret;
@@ -158,6 +324,7 @@ static int msm_gpio_remove(struct platform_device *dev)
if (ret < 0)
return ret;
+ free_irq(msm_gpio->irq_summary, msm_gpio);
kfree(msm_gpio);
return 0;
diff --git a/include/linux/msm7200a-gpio.h b/include/linux/msm7200a-gpio.h
index c44d16b..317c1fd 100644
--- a/include/linux/msm7200a-gpio.h
+++ b/include/linux/msm7200a-gpio.h
@@ -34,6 +34,11 @@
* @in: GPIO_IN_n
* @out: GPIO_OUT_n
* @oe: GPIO_OE_n
+ * @int_status: GPIO_INT_STATUS_n
+ * @int_clear: GPIO_INT_CLEAR_n
+ * @int_en: GPIO_INT_EN_n
+ * @int_edge: GPIO_INT_EDGE_n
+ * @int_pos: GPIO_INT_POS_n
*
* Registers are not guaranteed to be packed in memory, or even
* located in a predictable pattern.
@@ -42,6 +47,11 @@ struct msm7200a_gpio_regs {
void __iomem *in;
void __iomem *out;
void __iomem *oe;
+ void __iomem *int_status;
+ void __iomem *int_clear;
+ void __iomem *int_en;
+ void __iomem *int_edge;
+ void __iomem *int_pos;
};
/**
@@ -50,12 +60,27 @@ struct msm7200a_gpio_regs {
* directly to gpio_chip.base.
* @ngpio: The number of gpio lines to be managed by the device.
* Must be <= 32. Corresponds directly to gpio_chip.ngpio.
+ * @irq_base: The first irq to be assigned to the device. The gpio
+ * at 'gpio_base' will be assigned irq 'irq_base',
+ * gpio 'gpio_base + 1' will receive irq 'irq_base + 1',
+ * and so on.
+ * @irq_summary: The summary irq line which will be used by the device
+ * to notify the kernel when an interrupt occurs on
+ * any of its gpio lines. Most MSM SoCs have more
+ * than one gpio device sharing each of these.
+ * @latch_level_irqs: The MSM gpio hardware latches level interrupts,
+ * which is atypical. Setting this flag to false
+ * makes the driver compensate for this and produce
+ * the traditional unlatched behavior for level irqs.
* @regs: Addresses of the registers which control the gpios
* to be managed by the device.
*/
struct msm7200a_gpio_platform_data {
unsigned gpio_base;
unsigned ngpio;
+ unsigned irq_base;
+ unsigned irq_summary;
+ bool latch_level_irqs;
struct msm7200a_gpio_regs regs;
};
--
1.7.0.4
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
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2010-06-12 18:59 [PATCH 0/2 v3] gpio: msm7200a: Add gpiolib support for MSM chips Gregory Bean
2010-06-12 18:59 ` [PATCH 1/2 " Gregory Bean
2010-06-12 18:59 ` [PATCH 2/2 v3] gpio: msm7200a: Add irq support to msm-gpiolib Gregory Bean
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