From: Borislav Petkov <borislav.petkov@amd.com>
To: <akpm@linux-foundation.org>, <greg@kroah.com>, <mingo@elte.hu>
Cc: <norsk5@yahoo.com>, <tglx@linutronix.de>, <hpa@zytor.com>,
<mchehab@redhat.com>, <aris@redhat.com>,
edt@aei.ca, <linux-kernel@vger.kernel.org>,
Doug Thompson <dougthompson@xmission.com>,
Borislav Petkov <borislav.petkov@amd.com>
Subject: [PATCH 13/22] amd64_edac: add k8-specific methods
Date: Fri, 15 May 2009 14:22:24 +0200 [thread overview]
Message-ID: <1242390153-24493-14-git-send-email-borislav.petkov@amd.com> (raw)
In-Reply-To: <1242390153-24493-1-git-send-email-borislav.petkov@amd.com>
From: Doug Thompson <dougthompson@xmission.com>
Borislav:
- fix/cleanup/move comments
- fix function return value patterns
- cleanup debug calls
Reviewed-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Signed-off-by: Doug Thompson <dougthompson@xmission.com>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
---
drivers/edac/amd64_edac.c | 173 +++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 173 insertions(+), 0 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 5ec44a4..24c031f 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1013,3 +1013,176 @@ static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt)
return type;
}
+/*
+ * Read the DRAM Configuration Low register. It differs between CG, D & E revs
+ * and the later RevF memory controllers (DDR vs DDR2)
+ *
+ * Return:
+ * number of memory channels in operation
+ * Pass back:
+ * contents of the DCL0_LOW register
+ */
+static int k8_early_channel_count(struct amd64_pvt *pvt)
+{
+ int flag, err = 0;
+
+ err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0);
+ if (err)
+ return err;
+
+ if ((boot_cpu_data.x86_model >> 4) >= OPTERON_CPU_REV_F) {
+ /* RevF (NPT) and later */
+ flag = pvt->dclr0 & F10_WIDTH_128;
+ } else {
+ /* RevE and earlier */
+ flag = pvt->dclr0 & REVE_WIDTH_128;
+ }
+
+ /* not used */
+ pvt->dclr1 = 0;
+
+ return (flag) ? 2 : 1;
+}
+
+/* extract the ERROR ADDRESS for the K8 CPUs */
+static u64 k8_get_error_address(struct mem_ctl_info *mci,
+ struct amd64_error_info_regs *info)
+{
+ return (((u64) (info->nbeah & 0xff)) << 32) +
+ (info->nbeal & ~0x03);
+}
+
+/*
+ * Read the Base and Limit registers for K8 based Memory controllers; extract
+ * fields from the 'raw' reg into separate data fields
+ *
+ * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN
+ */
+static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
+{
+ u32 low;
+ u32 off = dram << 3; /* 8 bytes between DRAM entries */
+ int err;
+
+ err = pci_read_config_dword(pvt->addr_f1_ctl,
+ K8_DRAM_BASE_LOW + off, &low);
+ if (err)
+ debugf0("Reading K8_DRAM_BASE_LOW failed\n");
+
+ /* Extract parts into separate data entries */
+ pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8;
+ pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7;
+ pvt->dram_rw_en[dram] = (low & 0x3);
+
+ err = pci_read_config_dword(pvt->addr_f1_ctl,
+ K8_DRAM_LIMIT_LOW + off, &low);
+ if (err)
+ debugf0("Reading K8_DRAM_LIMIT_LOW failed\n");
+
+ /*
+ * Extract parts into separate data entries. Limit is the HIGHEST memory
+ * location of the region, so lower 24 bits need to be all ones
+ */
+ pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF;
+ pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7;
+ pvt->dram_DstNode[dram] = (low & 0x7);
+}
+
+static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
+ struct amd64_error_info_regs *info,
+ u64 SystemAddress)
+{
+ struct mem_ctl_info *src_mci;
+ unsigned short syndrome;
+ int channel, csrow;
+ u32 page, offset;
+
+ /* Extract the syndrome parts and form a 16-bit syndrome */
+ syndrome = EXTRACT_HIGH_SYNDROME(info->nbsl) << 8;
+ syndrome |= EXTRACT_LOW_SYNDROME(info->nbsh);
+
+ /* CHIPKILL enabled */
+ if (info->nbcfg & K8_NBCFG_CHIPKILL) {
+ channel = get_channel_from_ecc_syndrome(syndrome);
+ if (channel < 0) {
+ /*
+ * Syndrome didn't map, so we don't know which of the
+ * 2 DIMMs is in error. So we need to ID 'both' of them
+ * as suspect.
+ */
+ amd64_mc_printk(mci, KERN_WARNING,
+ "unknown syndrome 0x%x - possible error "
+ "reporting race\n", syndrome);
+ edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
+ return;
+ }
+ } else {
+ /*
+ * non-chipkill ecc mode
+ *
+ * The k8 documentation is unclear about how to determine the
+ * channel number when using non-chipkill memory. This method
+ * was obtained from email communication with someone at AMD.
+ * (Wish the email was placed in this comment - norsk)
+ */
+ channel = ((SystemAddress & BIT(3)) != 0);
+ }
+
+ /*
+ * Find out which node the error address belongs to. This may be
+ * different from the node that detected the error.
+ */
+ src_mci = find_mc_by_sys_addr(mci, SystemAddress);
+ if (src_mci) {
+ amd64_mc_printk(mci, KERN_ERR,
+ "failed to map error address 0x%lx to a node\n",
+ (unsigned long)SystemAddress);
+ edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
+ return;
+ }
+
+ /* Now map the SystemAddress to a CSROW */
+ csrow = sys_addr_to_csrow(src_mci, SystemAddress);
+ if (csrow < 0) {
+ edac_mc_handle_ce_no_info(src_mci, EDAC_MOD_STR);
+ } else {
+ error_address_to_page_and_offset(SystemAddress, &page, &offset);
+
+ edac_mc_handle_ce(src_mci, page, offset, syndrome, csrow,
+ channel, EDAC_MOD_STR);
+ }
+}
+
+/*
+ * determrine the number of PAGES in for this DIMM's size based on its DRAM
+ * Address Mapping.
+ *
+ * First step is to calc the number of bits to shift a value of 1 left to
+ * indicate show many pages. Start with the DBAM value as the starting bits,
+ * then proceed to adjust those shift bits, based on CPU rev and the table.
+ * See BKDG on the DBAM
+ */
+static int k8_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map)
+{
+ int nr_pages;
+
+ if (pvt->ext_model >= OPTERON_CPU_REV_F) {
+ nr_pages = 1 << (revf_quad_ddr2_shift[dram_map] - PAGE_SHIFT);
+ } else {
+ /*
+ * RevE and less section; this line is tricky. It collapses the
+ * table used by RevD and later to one that matches revisions CG
+ * and earlier.
+ */
+ dram_map -= (pvt->ext_model >= OPTERON_CPU_REV_D) ?
+ (dram_map > 8 ? 4 : (dram_map > 5 ?
+ 3 : (dram_map > 2 ? 1 : 0))) : 0;
+
+ /* 25 shift is 32MiB minimum DIMM size in RevE and prior */
+ nr_pages = 1 << (dram_map + 25 - PAGE_SHIFT);
+ }
+
+ return nr_pages;
+}
+
+
--
1.6.2.4
next prev parent reply other threads:[~2009-05-15 12:27 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-05-15 12:22 [RFC PATCH 00/21 v4] amd64_edac: EDAC module for AMD64 Borislav Petkov
2009-05-15 12:22 ` [PATCH 01/22] x86: add methods for writing of an MSR on several CPUs Borislav Petkov
2009-05-19 17:24 ` Borislav Petkov
2009-05-20 5:18 ` H. Peter Anvin
2009-05-20 14:49 ` Borislav Petkov
2009-05-20 21:39 ` H. Peter Anvin
2009-05-21 14:08 ` Borislav Petkov
2009-05-21 14:21 ` H. Peter Anvin
2009-05-21 16:26 ` Borislav Petkov
2009-05-21 17:38 ` H. Peter Anvin
2009-05-22 14:39 ` Borislav Petkov
2009-05-22 16:47 ` H. Peter Anvin
2009-05-25 11:01 ` Borislav Petkov
2009-05-25 11:02 ` Borislav Petkov
2009-05-25 11:03 ` Borislav Petkov
2009-05-15 12:22 ` [PATCH 02/22] edac: fold __func__ into edac_debug_printk Borislav Petkov
2009-05-15 13:25 ` Mauro Carvalho Chehab
2009-05-15 12:22 ` [PATCH 03/22] amd64_edac: add driver header Borislav Petkov
2009-05-15 12:22 ` [PATCH 04/22] amd64_edac: add debugging/testing code Borislav Petkov
2009-05-15 12:22 ` [PATCH 05/22] amd64_edac: add DRAM error injection logic using sysfs Borislav Petkov
2009-05-15 12:22 ` [PATCH 06/22] amd64_edac: add MCA error types Borislav Petkov
2009-05-15 12:22 ` [PATCH 07/22] amd64_edac: add memory scrubber interface Borislav Petkov
2009-05-15 12:22 ` [PATCH 08/22] amd64_edac: add sys addr to memory controller mapping helpers Borislav Petkov
2009-05-15 12:22 ` [PATCH 09/22] amd64_edac: add functionality to compute the DRAM hole Borislav Petkov
2009-05-15 12:22 ` [PATCH 10/22] amd64_edac: add DRAM address type conversion facilities Borislav Petkov
2009-05-15 12:22 ` [PATCH 11/22] amd64_edac: add helper to dump relevant registers Borislav Petkov
2009-05-15 12:22 ` [PATCH 12/22] amd64_edac: assign DRAM chip select base and mask in a family-specific way Borislav Petkov
2009-05-15 12:22 ` Borislav Petkov [this message]
2009-05-15 12:22 ` [PATCH 14/22] amd64_edac: add F10h-and-later methods-p1 Borislav Petkov
2009-05-15 12:22 ` [PATCH 15/22] amd64_edac: add F10h-and-later methods-p2 Borislav Petkov
2009-05-15 12:22 ` [PATCH 16/22] amd64_edac: add F10h-and-later methods-p3 Borislav Petkov
2009-05-15 12:22 ` [PATCH 17/22] amd64_edac: add per-family descriptors Borislav Petkov
2009-05-15 12:22 ` [PATCH 18/22] amd64_edac: add ECC chipkill syndrome mapping table Borislav Petkov
2009-05-15 12:22 ` [PATCH 19/22] amd64_edac: add error decoding logic Borislav Petkov
2009-05-15 12:22 ` [PATCH 20/22] amd64_edac: add EDAC core-related initializers Borislav Petkov
2009-05-15 12:22 ` [PATCH 21/22] amd64_edac: add ECC reporting initializers Borislav Petkov
2009-05-15 12:22 ` [PATCH 22/22] amd64_edac: add module registration routines Borislav Petkov
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