From: Borislav Petkov <borislav.petkov@amd.com>
To: <akpm@linux-foundation.org>, <greg@kroah.com>, <mingo@elte.hu>
Cc: <norsk5@yahoo.com>, <tglx@linutronix.de>, <hpa@zytor.com>,
<mchehab@redhat.com>, <aris@redhat.com>,
edt@aei.ca, <linux-kernel@vger.kernel.org>,
Doug Thompson <dougthompson@xmission.com>,
Borislav Petkov <borislav.petkov@amd.com>
Subject: [PATCH 11/22] amd64_edac: add helper to dump relevant registers
Date: Fri, 15 May 2009 14:22:22 +0200 [thread overview]
Message-ID: <1242390153-24493-12-git-send-email-borislav.petkov@amd.com> (raw)
In-Reply-To: <1242390153-24493-1-git-send-email-borislav.petkov@amd.com>
From: Doug Thompson <dougthompson@xmission.com>
Borislav:
- cleanup/fix comments
- fix function return value patterns
- cleanup dbg calls
Reviewed-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Signed-off-by: Doug Thompson <dougthompson@xmission.com>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
---
drivers/edac/amd64_edac.c | 142 +++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 142 insertions(+), 0 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 28f85c9..3d6d000 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -729,3 +729,145 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
return csrow;
}
+static int get_channel_from_ecc_syndrome(unsigned short syndrome);
+
+static void amd64_cpu_display_info(struct amd64_pvt *pvt)
+{
+ if (boot_cpu_data.x86 == 0x11)
+ edac_printk(KERN_DEBUG, EDAC_MC, "F11h CPU detected\n");
+ else if (boot_cpu_data.x86 == 0x10)
+ edac_printk(KERN_DEBUG, EDAC_MC, "F10h CPU detected\n");
+ else if (boot_cpu_data.x86 == 0xf)
+ edac_printk(KERN_DEBUG, EDAC_MC, "%s detected\n",
+ (pvt->ext_model >= OPTERON_CPU_REV_F) ?
+ "Rev F or later" : "Rev E or earlier");
+ else
+ /* we'll hardly ever ever get here */
+ edac_printk(KERN_ERR, EDAC_MC, "Unknown cpu!\n");
+}
+
+/*
+ * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
+ * are ECC capable.
+ */
+static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt)
+{
+ int bit;
+ enum dev_type edac_cap = EDAC_NONE;
+
+ bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= OPTERON_CPU_REV_F)
+ ? 19
+ : 17;
+
+ if (pvt->dclr0 >> BIT(bit))
+ edac_cap = EDAC_FLAG_SECDED;
+
+ return edac_cap;
+}
+
+
+static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt,
+ int ganged);
+
+/* Display and decode various NB registers for debug purposes. */
+static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
+{
+ int ganged;
+
+ debugf1(" nbcap:0x%8.08x DctDualCap=%s DualNode=%s 8-Node=%s\n",
+ pvt->nbcap,
+ (pvt->nbcap & K8_NBCAP_DCT_DUAL) ? "True" : "False",
+ (pvt->nbcap & K8_NBCAP_DUAL_NODE) ? "True" : "False",
+ (pvt->nbcap & K8_NBCAP_8_NODE) ? "True" : "False");
+ debugf1(" ECC Capable=%s ChipKill Capable=%s\n",
+ (pvt->nbcap & K8_NBCAP_SECDED) ? "True" : "False",
+ (pvt->nbcap & K8_NBCAP_CHIPKILL) ? "True" : "False");
+ debugf1(" DramCfg0-low=0x%08x DIMM-ECC=%s Parity=%s Width=%s\n",
+ pvt->dclr0,
+ (pvt->dclr0 & BIT(19)) ? "Enabled" : "Disabled",
+ (pvt->dclr0 & BIT(8)) ? "Enabled" : "Disabled",
+ (pvt->dclr0 & BIT(11)) ? "128b" : "64b");
+ debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s DIMM Type=%s\n",
+ (pvt->dclr0 & BIT(12)) ? "Y" : "N",
+ (pvt->dclr0 & BIT(13)) ? "Y" : "N",
+ (pvt->dclr0 & BIT(14)) ? "Y" : "N",
+ (pvt->dclr0 & BIT(15)) ? "Y" : "N",
+ (pvt->dclr0 & BIT(16)) ? "UN-Buffered" : "Buffered");
+
+
+ debugf1(" online-spare: 0x%8.08x\n", pvt->online_spare);
+
+ if (boot_cpu_data.x86 == 0xf) {
+ debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n",
+ pvt->dhar, dhar_base(pvt->dhar),
+ k8_dhar_offset(pvt->dhar));
+ debugf1(" DramHoleValid=%s\n",
+ (pvt->dhar & DHAR_VALID) ? "True" : "False");
+
+ debugf1(" dbam-dkt: 0x%8.08x\n", pvt->dbam0);
+
+ /* everything below this point is Fam10h and above */
+ return;
+
+ } else {
+ debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n",
+ pvt->dhar, dhar_base(pvt->dhar),
+ f10_dhar_offset(pvt->dhar));
+ debugf1(" DramMemHoistValid=%s DramHoleValid=%s\n",
+ (pvt->dhar & F10_DRAM_MEM_HOIST_VALID) ?
+ "True" : "False",
+ (pvt->dhar & DHAR_VALID) ?
+ "True" : "False");
+ }
+
+ /* Only if NOT ganged does dcl1 have valid info */
+ if (!dct_ganging_enabled(pvt)) {
+ debugf1(" DramCfg1-low=0x%08x DIMM-ECC=%s Parity=%s "
+ "Width=%s\n", pvt->dclr1,
+ (pvt->dclr1 & BIT(19)) ? "Enabled" : "Disabled",
+ (pvt->dclr1 & BIT(8)) ? "Enabled" : "Disabled",
+ (pvt->dclr1 & BIT(11)) ? "128b" : "64b");
+ debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s "
+ "DIMM Type=%s\n",
+ (pvt->dclr1 & BIT(12)) ? "Y" : "N",
+ (pvt->dclr1 & BIT(13)) ? "Y" : "N",
+ (pvt->dclr1 & BIT(14)) ? "Y" : "N",
+ (pvt->dclr1 & BIT(15)) ? "Y" : "N",
+ (pvt->dclr1 & BIT(16)) ? "UN-Buffered" : "Buffered");
+ }
+
+ /*
+ * Determine if ganged and then dump memory sizes for first controller,
+ * and if NOT ganged dump info for 2nd controller.
+ */
+ ganged = dct_ganging_enabled(pvt);
+
+ f10_debug_display_dimm_sizes(0, pvt, ganged);
+
+ if (!ganged)
+ f10_debug_display_dimm_sizes(1, pvt, ganged);
+}
+
+/* Read in both of DBAM registers */
+static void amd64_read_dbam_reg(struct amd64_pvt *pvt)
+{
+ int err = 0;
+ unsigned int reg;
+
+ reg = DBAM0;
+ err = pci_read_config_dword(pvt->dram_f2_ctl, reg, &pvt->dbam0);
+ if (err)
+ goto err_reg;
+
+ if (boot_cpu_data.x86 >= 0x10) {
+ reg = DBAM1;
+ err = pci_read_config_dword(pvt->dram_f2_ctl, reg, &pvt->dbam1);
+
+ if (err)
+ goto err_reg;
+ }
+
+err_reg:
+ debugf0("Error reading F2x%03x.\n", reg);
+}
+
--
1.6.2.4
next prev parent reply other threads:[~2009-05-15 12:28 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-05-15 12:22 [RFC PATCH 00/21 v4] amd64_edac: EDAC module for AMD64 Borislav Petkov
2009-05-15 12:22 ` [PATCH 01/22] x86: add methods for writing of an MSR on several CPUs Borislav Petkov
2009-05-19 17:24 ` Borislav Petkov
2009-05-20 5:18 ` H. Peter Anvin
2009-05-20 14:49 ` Borislav Petkov
2009-05-20 21:39 ` H. Peter Anvin
2009-05-21 14:08 ` Borislav Petkov
2009-05-21 14:21 ` H. Peter Anvin
2009-05-21 16:26 ` Borislav Petkov
2009-05-21 17:38 ` H. Peter Anvin
2009-05-22 14:39 ` Borislav Petkov
2009-05-22 16:47 ` H. Peter Anvin
2009-05-25 11:01 ` Borislav Petkov
2009-05-25 11:02 ` Borislav Petkov
2009-05-25 11:03 ` Borislav Petkov
2009-05-15 12:22 ` [PATCH 02/22] edac: fold __func__ into edac_debug_printk Borislav Petkov
2009-05-15 13:25 ` Mauro Carvalho Chehab
2009-05-15 12:22 ` [PATCH 03/22] amd64_edac: add driver header Borislav Petkov
2009-05-15 12:22 ` [PATCH 04/22] amd64_edac: add debugging/testing code Borislav Petkov
2009-05-15 12:22 ` [PATCH 05/22] amd64_edac: add DRAM error injection logic using sysfs Borislav Petkov
2009-05-15 12:22 ` [PATCH 06/22] amd64_edac: add MCA error types Borislav Petkov
2009-05-15 12:22 ` [PATCH 07/22] amd64_edac: add memory scrubber interface Borislav Petkov
2009-05-15 12:22 ` [PATCH 08/22] amd64_edac: add sys addr to memory controller mapping helpers Borislav Petkov
2009-05-15 12:22 ` [PATCH 09/22] amd64_edac: add functionality to compute the DRAM hole Borislav Petkov
2009-05-15 12:22 ` [PATCH 10/22] amd64_edac: add DRAM address type conversion facilities Borislav Petkov
2009-05-15 12:22 ` Borislav Petkov [this message]
2009-05-15 12:22 ` [PATCH 12/22] amd64_edac: assign DRAM chip select base and mask in a family-specific way Borislav Petkov
2009-05-15 12:22 ` [PATCH 13/22] amd64_edac: add k8-specific methods Borislav Petkov
2009-05-15 12:22 ` [PATCH 14/22] amd64_edac: add F10h-and-later methods-p1 Borislav Petkov
2009-05-15 12:22 ` [PATCH 15/22] amd64_edac: add F10h-and-later methods-p2 Borislav Petkov
2009-05-15 12:22 ` [PATCH 16/22] amd64_edac: add F10h-and-later methods-p3 Borislav Petkov
2009-05-15 12:22 ` [PATCH 17/22] amd64_edac: add per-family descriptors Borislav Petkov
2009-05-15 12:22 ` [PATCH 18/22] amd64_edac: add ECC chipkill syndrome mapping table Borislav Petkov
2009-05-15 12:22 ` [PATCH 19/22] amd64_edac: add error decoding logic Borislav Petkov
2009-05-15 12:22 ` [PATCH 20/22] amd64_edac: add EDAC core-related initializers Borislav Petkov
2009-05-15 12:22 ` [PATCH 21/22] amd64_edac: add ECC reporting initializers Borislav Petkov
2009-05-15 12:22 ` [PATCH 22/22] amd64_edac: add module registration routines Borislav Petkov
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