From: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
To: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
<linux-riscv@lists.infradead.org>, <linux-spi@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
<valentina.fernandezalanis@microchip.com>,
<prajna.rajendrakumar@microchip.com>
Subject: [PATCH v2 0/3] Add support for GPIO based CS
Date: Tue, 14 May 2024 11:45:05 +0100 [thread overview]
Message-ID: <20240514104508.938448-1-prajna.rajendrakumar@microchip.com> (raw)
The Microchip PolarFire SoC SPI "hard" controller supports eight
chip selects. However, only one chip select is physically wired.
Therefore, use GPIO descriptors to configure additional chip select
lines.
v1-> v2:
- Modified all commit messages for better understanding
- driver - added spi_is_csgpiod() API to address review comment
- bindings - fixed bindings to set the default value of num-cs
Prajna Rajendra Kumar (3):
spi: dt-bindings: Add num-cs property for mpfs-spi
spi: spi-microchip-core: Fix the number of chip selects supported
spi: spi-microchip-core: Add support for GPIO based CS
.../bindings/spi/microchip,mpfs-spi.yaml | 29 +++++++++++++++++--
drivers/spi/spi-microchip-core.c | 6 +++-
2 files changed, 31 insertions(+), 4 deletions(-)
--
2.25.1
next reply other threads:[~2024-05-14 10:45 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-14 10:45 Prajna Rajendra Kumar [this message]
2024-05-14 10:45 ` [PATCH v2 1/3] spi: dt-bindings: Add num-cs property for mpfs-spi Prajna Rajendra Kumar
2024-05-14 17:52 ` Conor Dooley
2024-05-14 10:45 ` [PATCH v2 2/3] spi: spi-microchip-core: Fix the number of chip selects supported Prajna Rajendra Kumar
2024-05-14 17:53 ` Conor Dooley
2024-05-14 10:45 ` [PATCH v2 3/3] spi: spi-microchip-core: Add support for GPIO based CS Prajna Rajendra Kumar
2024-05-14 17:57 ` Conor Dooley
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