From: Palmer Dabbelt <palmer@dabbelt.com>
To: Conor Dooley <conor@kernel.org>
Cc: linux-sparse@vger.kernel.org, Conor Dooley <conor@kernel.org>,
Conor Dooley <conor.dooley@microchip.com>,
luc.vanoostenryck@gmail.com, linux-riscv@lists.infradead.org
Subject: Re: [PATCH v1] RISC-V: Add basic support for the vector extension
Date: Mon, 06 Mar 2023 14:29:21 -0800 (PST) [thread overview]
Message-ID: <mhng-ac1d596b-0748-4dab-8161-80c8d5537db2@palmer-ri-x1c9a> (raw)
In-Reply-To: <20230306222321.1992900-1-conor@kernel.org>
On Mon, 06 Mar 2023 14:23:22 PST (-0800), Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> I've started hitting this in CI while testing Andy's vector enablement
> series. I'm not entirely sure if there is more to do here, other than
> squeezing in the duplicate of what has been done for other extensions.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> This is based on top of patches already on the sparse list, adding
> support for some multi-letter extensions for RISC-V:
> https://lore.kernel.org/linux-sparse/20220811033138.20676-1-palmer@rivosinc.com/
> https://lore.kernel.org/linux-sparse/20220811052957.16634-1-palmer@rivosinc.com/
>
> CC: luc.vanoostenryck@gmail.com
> CC: palmer@dabbelt.com
> CC: linux-sparse@vger.kernel.org
> CC: linux-riscv@lists.infradead.org
> ---
> target-riscv.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target-riscv.c b/target-riscv.c
> index 8338d7a6..c8282814 100644
> --- a/target-riscv.c
> +++ b/target-riscv.c
> @@ -21,6 +21,7 @@
> #define RISCV_ZIFENCEI (1 << 11)
> #define RISCV_ZICBOM (1 << 12)
> #define RISCV_ZIHINTPAUSE (1 << 13)
> +#define RISCV_VECTOR (1 << 14)
>
> static unsigned int riscv_flags;
>
> @@ -41,6 +42,7 @@ static void parse_march_riscv(const char *arg)
> { "f", RISCV_FLOAT|RISCV_FDIV|RISCV_ZICSR },
> { "d", RISCV_DOUBLE|RISCV_FDIV|RISCV_ZICSR },
> { "c", RISCV_COMP },
> + { "v", RISCV_VECTOR },
> { "_zicsr", RISCV_ZICSR },
> { "_zifencei", RISCV_ZIFENCEI },
> { "_zicbom", RISCV_ZICBOM },
> @@ -147,6 +149,8 @@ static void predefine_riscv(const struct target *self)
> predefine("__riscv_zicbom", 1, "1");
> if (riscv_flags & RISCV_ZIHINTPAUSE)
> predefine("__riscv_zihintpause", 1, "1");
> + if (riscv_flags & RISCV_VECTOR)
> + predefine("__riscv_vector", 1, "1");
V adds a bunch of V-subset extensions. I don't think we need to
faithfully handle those, but we should at least set the right element
type and length fields for V as code might depend on those.
>
> if (cmodel)
> predefine_strong("__riscv_cmodel_%s", cmodel);
prev parent reply other threads:[~2023-03-06 22:29 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-06 22:23 [PATCH v1] RISC-V: Add basic support for the vector extension Conor Dooley
2023-03-06 22:29 ` Palmer Dabbelt [this message]
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