From: Thomas Gleixner <tglx@linutronix.de>
To: Guenter Roeck <linux@roeck-us.net>
Cc: LKML <linux-kernel@vger.kernel.org>,
x86@kernel.org, Linus Torvalds <torvalds@linuxfoundation.org>,
Uros Bizjak <ubizjak@gmail.com>,
linux-sparse@vger.kernel.org, lkp@intel.com,
oe-kbuild-all@lists.linux.dev
Subject: Re: [patch 5/9] x86: Cure per CPU madness on UP
Date: Thu, 21 Mar 2024 12:14:27 +0100 [thread overview]
Message-ID: <87r0g3hm5o.ffs@tglx> (raw)
In-Reply-To: <d51ec9a1-5221-4005-9980-8258df8b5102@roeck-us.net>
On Wed, Mar 20 2024 at 08:46, Guenter Roeck wrote:
> On 3/20/24 01:58, Thomas Gleixner wrote:
>> On Fri, Mar 15 2024 at 09:17, Guenter Roeck wrote:
>>> I don't know the code well enough to determine what is wrong.
>>> Please let me know what I can do to help debugging the problem.
>>
>> Could you provide me the config and the qemu command line?
>>
>
> defconfig-CONFIG_SMP and
>
> qemu-system-x86_64 -kernel arch/x86/boot/bzImage -cpu Haswell \
> --append "console=ttyS0" -nographic -monitor none
>
> The cpu doesn't really matter as long as it is an Intel CPU.
> A root file system isn't needed since the boot doesn't get that far.
Now it get's interesting because I can't reproduce it with that setup at
all.
What's weird is that I saw it exactly once on 64-bit in a VM with a UP
config two days ago, but when I started to add instrumentation it never
came back even after backing the instrumentation changes out. I have
seriously no idea what's going on there.
Is it fully reproducible on your side?
If so can you please provide a full dmesg and then apply the patch below
and provide the resulting full dmesg too?
I found two other issues while trying to find a way to reproduce, but
those are completely unrelated to the problem you are observing.
Thanks,
tglx
---
arch/x86/kernel/cpu/topology.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
--- a/arch/x86/kernel/cpu/topology.c
+++ b/arch/x86/kernel/cpu/topology.c
@@ -176,6 +176,8 @@ static __init void topo_register_apic(u3
{
int cpu, dom;
+ pr_info("APIC: %x %d\n", apic_id, present);
+
if (present) {
set_bit(apic_id, phys_cpu_present_map);
@@ -277,10 +279,23 @@ int topology_get_logical_id(u32 apicid,
/* Remove the bits below @at_level to get the proper level ID of @apicid */
unsigned int lvlid = topo_apicid(apicid, at_level);
- if (lvlid >= MAX_LOCAL_APIC)
+ pr_info("APIC logical ID: %x %x %d\n", apicid, lvlid, at_level);
+
+ if (WARN_ON_ONCE(lvlid >= MAX_LOCAL_APIC))
return -ERANGE;
- if (!test_bit(lvlid, apic_maps[at_level].map))
+
+ /*
+ * If there was no APIC registered, then the map check below would
+ * fail. With no APIC this is guaranteed to be an UP system and
+ * therefore all topology levels have only one entry and their
+ * logical ID is obviously 0.
+ */
+ if (topo_info.boot_cpu_apic_id == BAD_APICID)
+ return 0;
+
+ if (WARN_ON_ONCE(!test_bit(lvlid, apic_maps[at_level].map)))
return -ENODEV;
+
/* Get the number of set bits before @lvlid. */
return bitmap_weight(apic_maps[at_level].map, lvlid);
}
next prev parent reply other threads:[~2024-03-21 11:14 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-04 10:12 [patch 0/9] x86: Cure tons of sparse warnings (mostly __percpu) Thomas Gleixner
2024-03-04 10:12 ` [patch 1/9] perf/x86/amd/uncore: Fix __percpu annotation Thomas Gleixner
2024-03-04 10:12 ` [patch 2/9] x86/msr: Prepare for including percpu.h Thomas Gleixner
2024-03-04 10:12 ` [patch 3/9] x86/msr: Add missing __percpu annotations Thomas Gleixner
2024-03-04 10:12 ` [patch 4/9] smp: Consolidate smp_prepare_boot_cpu() Thomas Gleixner
2024-03-04 10:12 ` [patch 5/9] x86: Cure per CPU madness on UP Thomas Gleixner
2024-03-15 16:17 ` Guenter Roeck
2024-03-15 16:42 ` Linus Torvalds
2024-03-15 17:02 ` Guenter Roeck
2024-03-15 17:40 ` Thomas Gleixner
2024-03-15 22:55 ` Thomas Gleixner
2024-03-15 23:23 ` Linus Torvalds
2024-03-16 1:11 ` Thomas Gleixner
2024-03-16 1:23 ` Linus Torvalds
2024-03-16 21:34 ` Arnd Bergmann
2024-03-17 21:03 ` David Laight
2024-03-18 11:11 ` Thomas Gleixner
2024-03-18 17:27 ` Thomas Gleixner
2024-03-18 19:13 ` Arnd Bergmann
2024-03-19 16:21 ` Thomas Gleixner
2024-03-19 18:26 ` Guenter Roeck
2024-03-16 0:56 ` Guenter Roeck
2024-03-20 8:58 ` Thomas Gleixner
2024-03-20 15:46 ` Guenter Roeck
2024-03-21 11:14 ` Thomas Gleixner [this message]
2024-03-21 14:06 ` Guenter Roeck
2024-03-21 16:49 ` Thomas Gleixner
2024-03-04 10:12 ` [patch 6/9] x86/uaccess: Add missing __force to casts in __access_ok() and valid_user_address() Thomas Gleixner
2024-03-04 10:12 ` [patch 7/9] x86/cpu: Use EXPORT_PER_CPU_SYMBOL_GPL() for x86_spec_ctrl_current Thomas Gleixner
2024-03-04 10:12 ` [patch 8/9] x86/cpu: Provide a declaration for itlb_multihit_kvm_mitigation Thomas Gleixner
2024-03-04 10:12 ` [patch 9/9] x86/callthunks: Use EXPORT_PER_CPU_SYMBOL_GPL() for per CPU variables Thomas Gleixner
2024-03-04 11:08 ` [patch 0/9] x86: Cure tons of sparse warnings (mostly __percpu) Ingo Molnar
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