From: Pavel.Kozlov@synopsys.com
To: linux-snps-arc@lists.infradead.org
Subject: [PATCH] ARC: fix compile time assert fail for the config with PAE40 and 4K pages
Date: Fri, 10 Feb 2023 19:15:12 +0400 [thread overview]
Message-ID: <20230210151512.4712-1-kozlov@synopsys.com> (raw)
From: Pavel Kozlov <pavel.kozlov@synopsys.com>
Add support for the configuration with 4K Page Size and enabled ARC_PAE40.
Set two-level Page Table to 10:9:12, as with PAE40 a 4k page can settle
only 512 entries (with PAE40 size of PTE entry increases from 4 to 8
bytes).
In this configuration the Page Table can describe only 31-bit (2Gb) virtual
space, but it is not a problem as the ARC MMUv4 supports only 2Gb of
virtual address.
This patch doesn't affect other configurations.
Patch fixes compile time assert fail:
include/linux/compiler_types.h:328:45: error:
call to '__compiletime_assert_288' declared with attribute error:
BUILD_BUG_ON failed: (PTRS_PER_PTE * sizeof(pte_t)) > PAGE_SIZE
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>
---
Added the same ARC_VADDR_BITS macro name as used in ARCv3 port.
The 4K Page Size and enabled PAE configuration was tested on nSIM:
load, allocation/free of all memory (low and high), user space
tests from glibc test suite (malloc, string).
arch/arc/include/asm/pgtable-levels.h | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/arch/arc/include/asm/pgtable-levels.h b/arch/arc/include/asm/pgtable-levels.h
index ef68758b69f7..3b6afee9c272 100644
--- a/arch/arc/include/asm/pgtable-levels.h
+++ b/arch/arc/include/asm/pgtable-levels.h
@@ -42,12 +42,22 @@
* (so 4K page can only have 1K entries: or 10 bits)
*/
#ifdef CONFIG_ARC_PAGE_SIZE_4K
+#ifdef CONFIG_ARC_HAS_PAE40
+/*
+ * For PAE40 and 4K page size set 10:9:12 Page Table
+ * (as with PAE40 4k page can only have 512 entries)
+ * Page Table can describe only 31-bit (2Gb) virtual space
+ */
+#define PGDIR_SHIFT 21
+#define ARC_VADDR_BITS 31
+#else
#define PGDIR_SHIFT 22
+#endif /* CONFIG_ARC_HAS_PAE40 */
#else
#define PGDIR_SHIFT 21
-#endif
+#endif /* CONFIG_ARC_PAGE_SIZE_4K */
-#endif
+#endif /* CONFIG_ARC_HUGEPAGE_16M */
#else /* CONFIG_PGTABLE_LEVELS != 2 */
@@ -67,9 +77,13 @@
#endif /* CONFIG_PGTABLE_LEVELS */
+#ifndef ARC_VADDR_BITS
+#define ARC_VADDR_BITS 32
+#endif
+
#define PGDIR_SIZE BIT(PGDIR_SHIFT)
#define PGDIR_MASK (~(PGDIR_SIZE - 1))
-#define PTRS_PER_PGD BIT(32 - PGDIR_SHIFT)
+#define PTRS_PER_PGD BIT(ARC_VADDR_BITS - PGDIR_SHIFT)
#if CONFIG_PGTABLE_LEVELS > 3
#define PUD_SIZE BIT(PUD_SHIFT)
--
2.25.1
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