From: Geert Uytterhoeven <geert+renesas@glider.be>
To: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Guenter Roeck <linux@roeck-us.net>,
qemu-devel@nongnu.org, linux-sh@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [PATCH RFC] hw/sh4/sh7750: Add STBCR/STBCR2 register support
Date: Wed, 18 Oct 2023 14:40:23 +0200 [thread overview]
Message-ID: <20231018124023.2927710-1-geert+renesas@glider.be> (raw)
The new Linux SH7750 clock driver uses the registers for power-down
mode control, causing a crash:
byte read to SH7750_STBCR_A7 (0x000000001fc00004) not supported
Aborted (core dumped)
Fix this by adding support for the Standby Control Registers STBCR and
STBCR2.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
[RFC PATCH v3 12/35] drivers/clk/renesas: clk-sh7750.c SH7750/7751 CPG driver.
https://lore.kernel.org/all/a772e1b6de89af22057d3af31cc03dcad7964fc7.1697199949.git.ysato@users.sourceforge.jp
Accesses to CLKSTP00 and CLKSTCLK00 (0xfe0a0000/0x1e0a0000 and
0xfe0a0008/0x1e0a0008) don't seem to cause any issues, although I can't
see immediately where they are handled?
---
hw/sh4/sh7750.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
index ebe0fd96d94ca17b..deeb83b4540bbf2b 100644
--- a/hw/sh4/sh7750.c
+++ b/hw/sh4/sh7750.c
@@ -59,6 +59,9 @@ typedef struct SH7750State {
uint16_t bcr3;
uint32_t bcr4;
uint16_t rfcr;
+ /* Power-Down Modes */
+ uint8_t stbcr;
+ uint8_t stbcr2;
/* PCMCIA controller */
uint16_t pcr;
/* IO ports */
@@ -219,7 +222,13 @@ static void ignore_access(const char *kind, hwaddr addr)
static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr)
{
+ SH7750State *s = opaque;
+
switch (addr) {
+ case SH7750_STBCR_A7:
+ return s->stbcr;
+ case SH7750_STBCR2_A7:
+ return s->stbcr2;
default:
error_access("byte read", addr);
abort();
@@ -318,14 +327,24 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
static void sh7750_mem_writeb(void *opaque, hwaddr addr,
uint32_t mem_value)
{
+ SH7750State *s = opaque;
if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
ignore_access("byte write", addr);
return;
}
- error_access("byte write", addr);
- abort();
+ switch (addr) {
+ case SH7750_STBCR_A7:
+ s->stbcr = mem_value;
+ return;
+ case SH7750_STBCR2_A7:
+ s->stbcr2 = mem_value;
+ return;
+ default:
+ error_access("byte write", addr);
+ abort();
+ }
}
static void sh7750_mem_writew(void *opaque, hwaddr addr,
--
2.34.1
next reply other threads:[~2023-10-18 12:40 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-18 12:40 Geert Uytterhoeven [this message]
2023-10-18 12:46 ` [PATCH RFC] hw/sh4/sh7750: Add STBCR/STBCR2 register support John Paul Adrian Glaubitz
2023-10-18 13:03 ` Geert Uytterhoeven
2023-10-19 2:03 ` Yoshinori Sato
2023-10-19 7:14 ` Geert Uytterhoeven
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